Commit e2b3f95b authored by Asad Kamal's avatar Asad Kamal Committed by Alex Deucher
Browse files

drm/amd/pm: Update pmfw headers for smu_v13_0_12 



Update pmfw headers for smu_v13_0_12 new messages & metrics table.
Static metrics table for frequency added, Separate metrics table
for smu_v13_0_12 added.

Signed-off-by: default avatarAsad Kamal <asad.kamal@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c94943b0

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h

+145 −2
Original line number Diff line number Diff line
@@ -38,6 +38,13 @@ 
#define NUM_SOC_P2S_TABLES    6

#define NUM_GFX_P2S_TABLES    8

#define NUM_PSM_DIDT_THRESHOLDS 3

#define NUM_XVMIN_VMIN_THRESHOLDS 3



#define PRODUCT_MODEL_NUMBER_LEN      20

#define PRODUCT_NAME_LEN              64

#define PRODUCT_SERIAL_LEN            20

#define PRODUCT_MANUFACTURER_NAME_LEN 32

#define PRODUCT_FRU_ID_LEN            32



typedef enum {

/*0*/   FEATURE_DATA_CALCULATION            = 0,
@@ -85,11 +92,11 @@ typedef enum { 


//enum for MPIO PCIe gen speed msgs

typedef enum {

  PCIE_LINK_SPEED_INDEX_TABLE_RESERVED,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN1,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN2,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN3,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN4,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM,

  PCIE_LINK_SPEED_INDEX_TABLE_GEN5,

  PCIE_LINK_SPEED_INDEX_TABLE_COUNT

} PCIE_LINK_SPEED_INDEX_TABLE_e;
@@ -126,13 +133,149 @@ typedef enum { 
  GFX_DVM_MARGIN_COUNT

} GFX_DVM_MARGIN_e;



#define SMU_VF_METRICS_TABLE_VERSION 0x3

#define SMU_METRICS_TABLE_VERSION 0x12



typedef struct __attribute__((packed, aligned(4))) {

  uint64_t AccumulationCounter;



  //TEMPERATURE

  uint32_t MaxSocketTemperature;

  uint32_t MaxVrTemperature;

  uint32_t MaxHbmTemperature;

  uint64_t MaxSocketTemperatureAcc;

  uint64_t MaxVrTemperatureAcc;

  uint64_t MaxHbmTemperatureAcc;



  //POWER

  uint32_t SocketPowerLimit;

  uint32_t SocketPower;



  //ENERGY

  uint64_t Timestamp;

  uint64_t SocketEnergyAcc;

  uint64_t XcdEnergyAcc;

  uint64_t AidEnergyAcc;

  uint64_t HbmEnergyAcc;



  //FREQUENCY

  uint32_t GfxclkFrequencyLimit;

  uint32_t FclkFrequency;

  uint32_t UclkFrequency;

  uint32_t SocclkFrequency[4];

  uint32_t VclkFrequency[4];

  uint32_t DclkFrequency[4];

  uint32_t LclkFrequency[4];

  uint64_t GfxclkFrequencyAcc[8];



  //FREQUENCY RANGE

  uint32_t MaxLclkDpmRange;

  uint32_t MinLclkDpmRange;



  //XGMI

  uint32_t XgmiWidth;

  uint32_t XgmiBitrate;

  uint64_t XgmiReadBandwidthAcc[8];

  uint64_t XgmiWriteBandwidthAcc[8];



  //ACTIVITY

  uint32_t SocketGfxBusy;

  uint32_t DramBandwidthUtilization;

  uint64_t SocketGfxBusyAcc;

  uint64_t DramBandwidthAcc;

  uint32_t MaxDramBandwidth;

  uint64_t DramBandwidthUtilizationAcc;

  uint64_t PcieBandwidthAcc[4];



  //THROTTLERS

  uint32_t ProchotResidencyAcc;

  uint32_t PptResidencyAcc;

  uint32_t SocketThmResidencyAcc;

  uint32_t VrThmResidencyAcc;

  uint32_t HbmThmResidencyAcc;

  uint32_t GfxLockXCDMak;



  // New Items at end to maintain driver compatibility

  uint32_t GfxclkFrequency[8];



  //XGMI Data tranfser size

  uint64_t XgmiReadDataSizeAcc[8];//in KByte

  uint64_t XgmiWriteDataSizeAcc[8];//in KByte



  //PCIE BW Data and error count

  uint32_t PcieBandwidth[4];

  uint32_t PCIeL0ToRecoveryCountAcc;      // The Pcie counter itself is accumulated

  uint32_t PCIenReplayAAcc;               // The Pcie counter itself is accumulated

  uint32_t PCIenReplayARolloverCountAcc;  // The Pcie counter itself is accumulated

  uint32_t PCIeNAKSentCountAcc;           // The Pcie counter itself is accumulated

  uint32_t PCIeNAKReceivedCountAcc;       // The Pcie counter itself is accumulated



  // VCN/JPEG ACTIVITY

  uint32_t VcnBusy[4];

  uint32_t JpegBusy[40];



  // PCIE LINK Speed and width

  uint32_t PCIeLinkSpeed;

  uint32_t PCIeLinkWidth;



  // PER XCD ACTIVITY

  uint32_t GfxBusy[8];

  uint64_t GfxBusyAcc[8];



  //PCIE BW Data and error count

  uint32_t PCIeOtherEndRecoveryAcc;       // The Pcie counter itself is accumulated



  //Total App Clock Counter

  uint64_t GfxclkBelowHostLimitPptAcc[8];

  uint64_t GfxclkBelowHostLimitThmAcc[8];

  uint64_t GfxclkBelowHostLimitTotalAcc[8];

  uint64_t GfxclkLowUtilizationAcc[8];

} MetricsTable_t;



#define SMU_VF_METRICS_TABLE_MASK (1 << 31)

#define SMU_VF_METRICS_TABLE_VERSION (0x6 | SMU_VF_METRICS_TABLE_MASK)



typedef struct __attribute__((packed, aligned(4))) {

  uint32_t AccumulationCounter;

  uint32_t InstGfxclk_TargFreq;

  uint64_t AccGfxclk_TargFreq;

  uint64_t AccGfxRsmuDpm_Busy;

  uint64_t AccGfxclkBelowHostLimitPpt;

  uint64_t AccGfxclkBelowHostLimitThm;

  uint64_t AccGfxclkBelowHostLimitTotal;

  uint64_t AccGfxclkLowUtilization;

} VfMetricsTable_t;



/* FRU product information */

typedef struct __attribute__((packed, aligned(4))) {

  uint8_t  ModelNumber[PRODUCT_MODEL_NUMBER_LEN];

  uint8_t  Name[PRODUCT_NAME_LEN];

  uint8_t  Serial[PRODUCT_SERIAL_LEN];

  uint8_t  ManufacturerName[PRODUCT_MANUFACTURER_NAME_LEN];

  uint8_t  FruId[PRODUCT_FRU_ID_LEN];

} FRUProductInfo_t;



#pragma pack(push, 4)

typedef struct {

  //FRU PRODUCT INFO

  FRUProductInfo_t  ProductInfo;



  //POWER

  uint32_t MaxSocketPowerLimit;



  //FREQUENCY RANGE

  uint32_t MaxGfxclkFrequency;

  uint32_t MinGfxclkFrequency;

  uint32_t FclkFrequencyTable[4];

  uint32_t UclkFrequencyTable[4];

  uint32_t SocclkFrequencyTable[4];

  uint32_t VclkFrequencyTable[4];

  uint32_t DclkFrequencyTable[4];

  uint32_t LclkFrequencyTable[4];



  //PSNs

  uint64_t PublicSerialNumber_AID[4];

  uint64_t PublicSerialNumber_XCD[8];

} StaticMetricsTable_t;

#pragma pack(pop)



#endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h

0 → 100644
+143 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef SMU_13_0_12_PPSMC_H

#define SMU_13_0_12_PPSMC_H



// SMU Response Codes:

#define PPSMC_Result_OK                             0x1

#define PPSMC_Result_Failed                         0xFF

#define PPSMC_Result_UnknownCmd                     0xFE

#define PPSMC_Result_CmdRejectedPrereq              0xFD

#define PPSMC_Result_CmdRejectedBusy                0xFC



// Message Definitions:

#define PPSMC_MSG_TestMessage                       0x1

#define PPSMC_MSG_GetSmuVersion                     0x2

#define PPSMC_MSG_GfxDriverReset                    0x3

#define PPSMC_MSG_GetDriverIfVersion                0x4

#define PPSMC_MSG_EnableAllSmuFeatures              0x5

#define PPSMC_MSG_DisableAllSmuFeatures             0x6

#define PPSMC_MSG_RequestI2cTransaction             0x7

#define PPSMC_MSG_GetMetricsVersion                 0x8

#define PPSMC_MSG_GetMetricsTable                   0x9

#define PPSMC_MSG_GetEccInfoTable                   0xA

#define PPSMC_MSG_GetEnabledSmuFeaturesLow          0xB

#define PPSMC_MSG_GetEnabledSmuFeaturesHigh         0xC

#define PPSMC_MSG_SetDriverDramAddrHigh             0xD

#define PPSMC_MSG_SetDriverDramAddrLow              0xE

#define PPSMC_MSG_SetToolsDramAddrHigh              0xF

#define PPSMC_MSG_SetToolsDramAddrLow               0x10

#define PPSMC_MSG_SetSystemVirtualDramAddrHigh      0x11

#define PPSMC_MSG_SetSystemVirtualDramAddrLow       0x12

#define PPSMC_MSG_SetSoftMinByFreq                  0x13

#define PPSMC_MSG_SetSoftMaxByFreq                  0x14

#define PPSMC_MSG_GetMinDpmFreq                     0x15

#define PPSMC_MSG_GetMaxDpmFreq                     0x16

#define PPSMC_MSG_GetDpmFreqByIndex                 0x17

#define PPSMC_MSG_SetPptLimit                       0x18

#define PPSMC_MSG_GetPptLimit                       0x19

#define PPSMC_MSG_DramLogSetDramAddrHigh            0x1A

#define PPSMC_MSG_DramLogSetDramAddrLow             0x1B

#define PPSMC_MSG_DramLogSetDramSize                0x1C

#define PPSMC_MSG_GetDebugData                      0x1D

#define PPSMC_MSG_HeavySBR                          0x1E

#define PPSMC_MSG_SetNumBadHbmPagesRetired          0x1F

#define PPSMC_MSG_DFCstateControl                   0x20

#define PPSMC_MSG_GetGmiPwrDnHyst                   0x21

#define PPSMC_MSG_SetGmiPwrDnHyst                   0x22

#define PPSMC_MSG_GmiPwrDnControl                   0x23

#define PPSMC_MSG_EnterGfxoff                       0x24

#define PPSMC_MSG_ExitGfxoff                        0x25

#define PPSMC_MSG_EnableDeterminism                 0x26

#define PPSMC_MSG_DisableDeterminism                0x27

#define PPSMC_MSG_DumpSTBtoDram                     0x28

#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh       0x29

#define PPSMC_MSG_STBtoDramLogSetDramAddrLow        0x2A

#define PPSMC_MSG_STBtoDramLogSetDramSize           0x2B

#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrHigh 0x2C

#define PPSMC_MSG_SetSystemVirtualSTBtoDramAddrLow  0x2D

#define PPSMC_MSG_GfxDriverResetRecovery            0x2E

#define PPSMC_MSG_TriggerVFFLR                      0x2F

#define PPSMC_MSG_SetSoftMinGfxClk                  0x30

#define PPSMC_MSG_SetSoftMaxGfxClk                  0x31

#define PPSMC_MSG_GetMinGfxDpmFreq                  0x32

#define PPSMC_MSG_GetMaxGfxDpmFreq                  0x33

#define PPSMC_MSG_PrepareForDriverUnload            0x34

#define PPSMC_MSG_ReadThrottlerLimit                0x35

#define PPSMC_MSG_QueryValidMcaCount                0x36

#define PPSMC_MSG_McaBankDumpDW                     0x37

#define PPSMC_MSG_GetCTFLimit                       0x38

#define PPSMC_MSG_ClearMcaOnRead                    0x39

#define PPSMC_MSG_QueryValidMcaCeCount              0x3A

#define PPSMC_MSG_McaBankCeDumpDW                   0x3B

#define PPSMC_MSG_SelectPLPDMode                    0x40

#define PPSMC_MSG_PmLogReadSample                   0x41

#define PPSMC_MSG_PmLogGetTableVersion              0x42

#define PPSMC_MSG_RmaDueToBadPageThreshold          0x43

#define PPSMC_MSG_SetThrottlingPolicy               0x44

#define PPSMC_MSG_SetPhaseDetectCSBWThreshold       0x45

#define PPSMC_MSG_SetPhaseDetectFreqHigh            0x46

#define PPSMC_MSG_SetPhaseDetectFreqLow             0x47

#define PPSMC_MSG_SetPhaseDetectDownHysterisis      0x48

#define PPSMC_MSG_SetPhaseDetectAlphaX1e6           0x49

#define PPSMC_MSG_SetPhaseDetectOnOff               0x4A

#define PPSMC_MSG_GetPhaseDetectResidency           0x4B

#define PPSMC_MSG_UpdatePccWaitDecMaxStr            0x4C

#define PPSMC_MSG_ResetSDMA                         0x4D

#define PPSMC_MSG_GetRasTableVersion                0x4E

#define PPSMC_MSG_GetRmaStatus                      0x4F

#define PPSMC_MSG_GetErrorCount                     0x50

#define PPSMC_MSG_GetBadPageCount                   0x51

#define PPSMC_MSG_GetBadPageInfo                    0x52

#define PPSMC_MSG_GetBadPagePaAddrLoHi              0x53

#define PPSMC_MSG_SetTimestampLoHi                  0x54

#define PPSMC_MSG_GetTimestampLoHi                  0x55

#define PPSMC_MSG_GetRasPolicy                      0x56

#define PPSMC_MSG_DumpErrorRecord                   0x57

#define PPSMC_MSG_EraseRasTable                     0x58

#define PPSMC_MSG_GetStaticMetricsTable             0x59

#define PPSMC_Message_Count                         0x5A



//PPSMC Reset Types for driver msg argument

#define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET        0x1

#define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET	      0x2

#define PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET        0x3



//PPSMC Reset Types for driver msg argument

#define PPSMC_THROTTLING_LIMIT_TYPE_SOCKET          0x1

#define PPSMC_THROTTLING_LIMIT_TYPE_HBM             0x2



//CTF/Throttle Limit types

#define PPSMC_AID_THM_TYPE                          0x1

#define PPSMC_CCD_THM_TYPE                          0x2

#define PPSMC_XCD_THM_TYPE                          0x3

#define PPSMC_HBM_THM_TYPE                          0x4



//PLPD modes

#define PPSMC_PLPD_MODE_DEFAULT                     0x1

#define PPSMC_PLPD_MODE_OPTIMIZED                   0x2



typedef uint32_t PPSMC_Result;

typedef uint32_t PPSMC_MSG;



#endif