Commit e2cb6926 authored by Chen Pei's avatar Chen Pei Committed by Paul Walmsley
Browse files

tools: riscv: Fixed misalignment of CSR related definitions 



The file tools/arch/riscv/include/asm/csr.h borrows from
arch/riscv/include/asm/csr.h, and subsequent modifications
related to CSR should maintain consistency.

Signed-off-by: default avatarChen Pei <cp0613@linux.alibaba.com>
Link: https://patch.msgid.link/20251114071215.816-1-cp0613@linux.alibaba.com


[pjw@kernel.org: dropped Fixes: lines for patches that weren't broken; removed superfluous blank line]
Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent 7b090e7b

drivers/perf/riscv_pmu_sbi.c

+1 −1
Original line number Diff line number Diff line
@@ -1109,7 +1109,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) 
			/* compute hardware counter index */

			hidx = info->csr - CSR_CYCLE;



		/* check if the corresponding bit is set in sscountovf or overflow mask in shmem */

		/* check if the corresponding bit is set in scountovf or overflow mask in shmem */

		if (!(overflow & BIT(hidx)))

			continue;

tools/arch/riscv/include/asm/csr.h

+3 −2
Original line number Diff line number Diff line
@@ -167,7 +167,8 @@ 
#define VSIP_TO_HVIP_SHIFT	(IRQ_VS_SOFT - IRQ_S_SOFT)

#define VSIP_VALID_MASK		((_AC(1, UL) << IRQ_S_SOFT) | \

				 (_AC(1, UL) << IRQ_S_TIMER) | \

				 (_AC(1, UL) << IRQ_S_EXT))

				 (_AC(1, UL) << IRQ_S_EXT) | \

				 (_AC(1, UL) << IRQ_PMU_OVF))



/* AIA CSR bits */

#define TOPI_IID_SHIFT		16
@@ -280,7 +281,7 @@ 
#define CSR_HPMCOUNTER30H	0xc9e

#define CSR_HPMCOUNTER31H	0xc9f



#define CSR_SSCOUNTOVF		0xda0

#define CSR_SCOUNTOVF		0xda0



#define CSR_SSTATUS		0x100

#define CSR_SIE			0x104