Unverified Commit e2ceac2f authored by Vijendar Mukunda's avatar Vijendar Mukunda Committed by Mark Brown
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ASoC: amd: ps: rename structure names, variable and other macros 



Rename macros and structure names, variable with ACP63 tag which are
specific to ACP6.3 platform.
Rename 'stream_index' and 'sdw_dma_data' variable names to avoid check
patch warnings.

Signed-off-by: default avatarVijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20250207062819.1527184-2-Vijendar.Mukunda@amd.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 6b8f162b

sound/soc/amd/ps/acp63.h

+34 −32
Original line number Diff line number Diff line
@@ -13,13 +13,13 @@ 
#define ACP63_REG_END		0x125C000



#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK	0x00010001

#define ACP_PGFSM_CNTL_POWER_ON_MASK	1

#define ACP_PGFSM_CNTL_POWER_OFF_MASK	0

#define ACP_PGFSM_STATUS_MASK		3

#define ACP_POWERED_ON			0

#define ACP_POWER_ON_IN_PROGRESS	1

#define ACP_POWERED_OFF		2

#define ACP_POWER_OFF_IN_PROGRESS	3

#define ACP63_PGFSM_CNTL_POWER_ON_MASK	1

#define ACP63_PGFSM_CNTL_POWER_OFF_MASK	0

#define ACP63_PGFSM_STATUS_MASK		3

#define ACP63_POWERED_ON			0

#define ACP63_POWER_ON_IN_PROGRESS	1

#define ACP63_POWERED_OFF		2

#define ACP63_POWER_OFF_IN_PROGRESS	3



#define ACP_ERROR_MASK 0x20000000

#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
@@ -60,7 +60,7 @@ 
#define AMD_SDW_MAX_MANAGERS		2



/* time in ms for acp timeout */

#define ACP_TIMEOUT		500

#define ACP63_TIMEOUT		500



#define ACP_SDW0_STAT			BIT(21)

#define ACP_SDW1_STAT			BIT(2)
@@ -72,13 +72,13 @@ 
#define ACP_AUDIO0_RX_THRESHOLD		0x1b

#define ACP_AUDIO1_RX_THRESHOLD		0x19

#define ACP_AUDIO2_RX_THRESHOLD		0x17

#define ACP_P1_AUDIO1_TX_THRESHOLD	BIT(6)

#define ACP_P1_AUDIO1_RX_THRESHOLD	BIT(5)

#define ACP_SDW_DMA_IRQ_MASK		0x1F800000

#define ACP_P1_SDW_DMA_IRQ_MASK		0x60

#define ACP63_P1_AUDIO1_TX_THRESHOLD	BIT(6)

#define ACP63_P1_AUDIO1_RX_THRESHOLD	BIT(5)

#define ACP63_SDW_DMA_IRQ_MASK		0x1F800000

#define ACP63_P1_SDW_DMA_IRQ_MASK	0x60

#define ACP63_SDW0_DMA_MAX_STREAMS	6

#define ACP63_SDW1_DMA_MAX_STREAMS	2

#define ACP_P1_AUDIO_TX_THRESHOLD	6

#define ACP63_P1_AUDIO_TX_THRESHOLD	6



/*

 * Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping
@@ -91,8 +91,8 @@ 
 * 4 (SDW0_AUDIO1_RX)	25

 * 5 (SDW0_AUDIO2_RX)	23

 */

#define SDW0_DMA_TX_IRQ_MASK(i)	(ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))

#define SDW0_DMA_RX_IRQ_MASK(i)	(ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))

#define ACP63_SDW0_DMA_TX_IRQ_MASK(i)	(ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))

#define ACP63_SDW0_DMA_RX_IRQ_MASK(i)	(ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))



/*

 * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping
@@ -101,7 +101,7 @@ 
 * 0 (SDW1_AUDIO1_TX)	6

 * 1 (SDW1_AUDIO1_RX)	5

 */

#define SDW1_DMA_IRQ_MASK(i)	(ACP_P1_AUDIO_TX_THRESHOLD - (i))

#define ACP63_SDW1_DMA_IRQ_MASK(i)	(ACP63_P1_AUDIO_TX_THRESHOLD - (i))



#define ACP_DELAY_US		5

#define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024)
@@ -148,18 +148,18 @@ enum acp_config { 
	ACP_CONFIG_15,

};



enum amd_sdw0_channel {

	ACP_SDW0_AUDIO0_TX = 0,

	ACP_SDW0_AUDIO1_TX,

	ACP_SDW0_AUDIO2_TX,

	ACP_SDW0_AUDIO0_RX,

	ACP_SDW0_AUDIO1_RX,

	ACP_SDW0_AUDIO2_RX,

enum amd_acp63_sdw0_channel {

	ACP63_SDW0_AUDIO0_TX = 0,

	ACP63_SDW0_AUDIO1_TX,

	ACP63_SDW0_AUDIO2_TX,

	ACP63_SDW0_AUDIO0_RX,

	ACP63_SDW0_AUDIO1_RX,

	ACP63_SDW0_AUDIO2_RX,

};



enum amd_sdw1_channel {

	ACP_SDW1_AUDIO1_TX,

	ACP_SDW1_AUDIO1_RX,

enum amd_acp63_sdw1_channel {

	ACP63_SDW1_AUDIO1_TX,

	ACP63_SDW1_AUDIO1_RX,

};



struct pdm_stream_instance {
@@ -180,8 +180,8 @@ struct pdm_dev_data { 
struct sdw_dma_dev_data {

	void __iomem *acp_base;

	struct mutex *acp_lock; /* used to protect acp common register access */

	struct snd_pcm_substream *sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS];

	struct snd_pcm_substream *sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS];

	struct snd_pcm_substream *acp63_sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS];

	struct snd_pcm_substream *acp63_sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS];

};



struct acp_sdw_dma_stream {
@@ -232,8 +232,10 @@ struct sdw_dma_ring_buf_reg { 
 * @addr: pci ioremap address

 * @reg_range: ACP reigister range

 * @acp_rev: ACP PCI revision id

 * @sdw0-dma_intr_stat: DMA interrupt status array for SoundWire manager-SW0 instance

 * @sdw_dma_intr_stat: DMA interrupt status array for SoundWire manager-SW1 instance

 * @acp63_sdw0-dma_intr_stat: DMA interrupt status array for ACP6.3 platform SoundWire

 * manager-SW0 instance

 * @acp63_sdw_dma_intr_stat: DMA interrupt status array for ACP6.3 platform SoundWire

 * manager-SW1 instance

 */



struct acp63_dev_data {
@@ -256,8 +258,8 @@ struct acp63_dev_data { 
	u32 addr;

	u32 reg_range;

	u32 acp_rev;

	u16 sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS];

	u16 sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS];

	u16 acp63_sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS];

	u16 acp63_sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS];

};



int snd_amd_acp_find_config(struct pci_dev *pci);

sound/soc/amd/ps/pci-ps.c

+32 −32
Original line number Diff line number Diff line
@@ -30,10 +30,10 @@ static int acp63_power_on(void __iomem *acp_base) 
	if (!val)

		return val;



	if ((val & ACP_PGFSM_STATUS_MASK) != ACP_POWER_ON_IN_PROGRESS)

		writel(ACP_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);

	if ((val & ACP63_PGFSM_STATUS_MASK) != ACP63_POWER_ON_IN_PROGRESS)

		writel(ACP63_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL);



	return readl_poll_timeout(acp_base + ACP_PGFSM_STATUS, val, !val, DELAY_US, ACP_TIMEOUT);

	return readl_poll_timeout(acp_base + ACP_PGFSM_STATUS, val, !val, DELAY_US, ACP63_TIMEOUT);

}



static int acp63_reset(void __iomem *acp_base)
@@ -45,13 +45,13 @@ static int acp63_reset(void __iomem *acp_base) 


	ret = readl_poll_timeout(acp_base + ACP_SOFT_RESET, val,

				 val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK,

				 DELAY_US, ACP_TIMEOUT);

				 DELAY_US, ACP63_TIMEOUT);

	if (ret)

		return ret;



	writel(0, acp_base + ACP_SOFT_RESET);



	return readl_poll_timeout(acp_base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP_TIMEOUT);

	return readl_poll_timeout(acp_base + ACP_SOFT_RESET, val, !val, DELAY_US, ACP63_TIMEOUT);

}



static void acp63_enable_interrupts(void __iomem *acp_base)
@@ -104,24 +104,24 @@ static int acp63_deinit(void __iomem *acp_base, struct device *dev) 


static irqreturn_t acp63_irq_thread(int irq, void *context)

{

	struct sdw_dma_dev_data *sdw_dma_data;

	struct sdw_dma_dev_data *sdw_data;

	struct acp63_dev_data *adata = context;

	u32 stream_index;

	u32 stream_id;



	sdw_dma_data = dev_get_drvdata(&adata->sdw_dma_dev->dev);

	sdw_data = dev_get_drvdata(&adata->sdw_dma_dev->dev);



	for (stream_index = 0; stream_index < ACP63_SDW0_DMA_MAX_STREAMS; stream_index++) {

		if (adata->sdw0_dma_intr_stat[stream_index]) {

			if (sdw_dma_data->sdw0_dma_stream[stream_index])

				snd_pcm_period_elapsed(sdw_dma_data->sdw0_dma_stream[stream_index]);

			adata->sdw0_dma_intr_stat[stream_index] = 0;

	for (stream_id = 0; stream_id < ACP63_SDW0_DMA_MAX_STREAMS; stream_id++) {

		if (adata->acp63_sdw0_dma_intr_stat[stream_id]) {

			if (sdw_data->acp63_sdw0_dma_stream[stream_id])

				snd_pcm_period_elapsed(sdw_data->acp63_sdw0_dma_stream[stream_id]);

			adata->acp63_sdw0_dma_intr_stat[stream_id] = 0;

		}

	}

	for (stream_index = 0; stream_index < ACP63_SDW1_DMA_MAX_STREAMS; stream_index++) {

		if (adata->sdw1_dma_intr_stat[stream_index]) {

			if (sdw_dma_data->sdw1_dma_stream[stream_index])

				snd_pcm_period_elapsed(sdw_dma_data->sdw1_dma_stream[stream_index]);

			adata->sdw1_dma_intr_stat[stream_index] = 0;

	for (stream_id = 0; stream_id < ACP63_SDW1_DMA_MAX_STREAMS; stream_id++) {

		if (adata->acp63_sdw1_dma_intr_stat[stream_id]) {

			if (sdw_data->acp63_sdw1_dma_stream[stream_id])

				snd_pcm_period_elapsed(sdw_data->acp63_sdw1_dma_stream[stream_id]);

			adata->acp63_sdw1_dma_intr_stat[stream_id] = 0;

		}

	}

	return IRQ_HANDLED;
@@ -180,48 +180,48 @@ static irqreturn_t acp63_irq_handler(int irq, void *dev_id) 
			snd_pcm_period_elapsed(ps_pdm_data->capture_stream);

		irq_flag = 1;

	}

	if (ext_intr_stat & ACP_SDW_DMA_IRQ_MASK) {

	if (ext_intr_stat & ACP63_SDW_DMA_IRQ_MASK) {

		for (index = ACP_AUDIO2_RX_THRESHOLD; index <= ACP_AUDIO0_TX_THRESHOLD; index++) {

			if (ext_intr_stat & BIT(index)) {

				writel(BIT(index), adata->acp63_base + ACP_EXTERNAL_INTR_STAT);

				switch (index) {

				case ACP_AUDIO0_TX_THRESHOLD:

					stream_id = ACP_SDW0_AUDIO0_TX;

					stream_id = ACP63_SDW0_AUDIO0_TX;

					break;

				case ACP_AUDIO1_TX_THRESHOLD:

					stream_id = ACP_SDW0_AUDIO1_TX;

					stream_id = ACP63_SDW0_AUDIO1_TX;

					break;

				case ACP_AUDIO2_TX_THRESHOLD:

					stream_id = ACP_SDW0_AUDIO2_TX;

					stream_id = ACP63_SDW0_AUDIO2_TX;

					break;

				case ACP_AUDIO0_RX_THRESHOLD:

					stream_id = ACP_SDW0_AUDIO0_RX;

					stream_id = ACP63_SDW0_AUDIO0_RX;

					break;

				case ACP_AUDIO1_RX_THRESHOLD:

					stream_id = ACP_SDW0_AUDIO1_RX;

					stream_id = ACP63_SDW0_AUDIO1_RX;

					break;

				case ACP_AUDIO2_RX_THRESHOLD:

					stream_id = ACP_SDW0_AUDIO2_RX;

					stream_id = ACP63_SDW0_AUDIO2_RX;

					break;

				}



				adata->sdw0_dma_intr_stat[stream_id] = 1;

				adata->acp63_sdw0_dma_intr_stat[stream_id] = 1;

				sdw_dma_irq_flag = 1;

			}

		}

	}



	if (ext_intr_stat1 & ACP_P1_AUDIO1_RX_THRESHOLD) {

		writel(ACP_P1_AUDIO1_RX_THRESHOLD,

	if (ext_intr_stat1 & ACP63_P1_AUDIO1_RX_THRESHOLD) {

		writel(ACP63_P1_AUDIO1_RX_THRESHOLD,

		       adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);

		adata->sdw1_dma_intr_stat[ACP_SDW1_AUDIO1_RX] = 1;

		adata->acp63_sdw1_dma_intr_stat[ACP63_SDW1_AUDIO1_RX] = 1;

		sdw_dma_irq_flag = 1;

	}



	if (ext_intr_stat1 & ACP_P1_AUDIO1_TX_THRESHOLD) {

		writel(ACP_P1_AUDIO1_TX_THRESHOLD,

	if (ext_intr_stat1 & ACP63_P1_AUDIO1_TX_THRESHOLD) {

		writel(ACP63_P1_AUDIO1_TX_THRESHOLD,

		       adata->acp63_base + ACP_EXTERNAL_INTR_STAT1);

		adata->sdw1_dma_intr_stat[ACP_SDW1_AUDIO1_TX] = 1;

		adata->acp63_sdw1_dma_intr_stat[ACP63_SDW1_AUDIO1_TX] = 1;

		sdw_dma_irq_flag = 1;

	}

sound/soc/amd/ps/ps-sdw-dma.c

+35 −37
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 


#define DRV_NAME "amd_ps_sdw_dma"



static struct sdw_dma_ring_buf_reg sdw0_dma_ring_buf_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {

static struct sdw_dma_ring_buf_reg acp63_sdw0_dma_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {

	{ACP_AUDIO0_TX_DMA_SIZE, ACP_AUDIO0_TX_FIFOADDR, ACP_AUDIO0_TX_FIFOSIZE,

	 ACP_AUDIO0_TX_RINGBUFSIZE, ACP_AUDIO0_TX_RINGBUFADDR, ACP_AUDIO0_TX_INTR_WATERMARK_SIZE,

	 ACP_AUDIO0_TX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO0_TX_LINEARPOSITIONCNTR_HIGH},
@@ -44,7 +44,7 @@ static struct sdw_dma_ring_buf_reg sdw0_dma_ring_buf_reg[ACP63_SDW0_DMA_MAX_STRE 
 * For TX/RX streams DMA registers programming for SDW1 instance, it uses ACP_P1_AUDIO1 register

 * set as per hardware register documentation

 */

static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP63_SDW1_DMA_MAX_STREAMS] =  {

static struct sdw_dma_ring_buf_reg acp63_sdw1_dma_reg[ACP63_SDW1_DMA_MAX_STREAMS] =  {

	{ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE,

	 ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR,

	 ACP_P1_AUDIO1_TX_INTR_WATERMARK_SIZE,
@@ -55,7 +55,7 @@ static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP63_SDW1_DMA_MAX_STRE 
	 ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_LOW, ACP_P1_AUDIO1_RX_LINEARPOSITIONCNTR_HIGH},

};



static u32 sdw0_dma_enable_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {

static u32 acp63_sdw0_dma_enable_reg[ACP63_SDW0_DMA_MAX_STREAMS] = {

	ACP_SW0_AUDIO0_TX_EN,

	ACP_SW0_AUDIO1_TX_EN,

	ACP_SW0_AUDIO2_TX_EN,
@@ -70,7 +70,7 @@ static u32 sdw0_dma_enable_reg[ACP63_SDW0_DMA_MAX_STREAMS] = { 
 * it uses ACP_SW1_AUDIO1_TX_EN and ACP_SW1_AUDIO1_RX_EN registers

 * as per hardware register documentation.

 */

static u32 sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = {

static u32 acp63_sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = {

	ACP_SW1_AUDIO1_TX_EN,

	ACP_SW1_AUDIO1_RX_EN,

};
@@ -117,8 +117,8 @@ static const struct snd_pcm_hardware acp63_sdw_hardware_capture = { 
static void acp63_enable_disable_sdw_dma_interrupts(void __iomem *acp_base, bool enable)

{

	u32 ext_intr_cntl, ext_intr_cntl1;

	u32 irq_mask = ACP_SDW_DMA_IRQ_MASK;

	u32 irq_mask1 = ACP_P1_SDW_DMA_IRQ_MASK;

	u32 irq_mask = ACP63_SDW_DMA_IRQ_MASK;

	u32 irq_mask1 = ACP63_P1_SDW_DMA_IRQ_MASK;



	if (enable) {

		ext_intr_cntl = readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
@@ -182,18 +182,18 @@ static int acp63_configure_sdw_ringbuffer(void __iomem *acp_base, u32 stream_id, 


	switch (manager_instance) {

	case ACP_SDW0:

		reg_dma_size = sdw0_dma_ring_buf_reg[stream_id].reg_dma_size;

		reg_fifo_addr =	sdw0_dma_ring_buf_reg[stream_id].reg_fifo_addr;

		reg_fifo_size = sdw0_dma_ring_buf_reg[stream_id].reg_fifo_size;

		reg_ring_buf_size = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_size;

		reg_ring_buf_addr = sdw0_dma_ring_buf_reg[stream_id].reg_ring_buf_addr;

		reg_dma_size = acp63_sdw0_dma_reg[stream_id].reg_dma_size;

		reg_fifo_addr =	acp63_sdw0_dma_reg[stream_id].reg_fifo_addr;

		reg_fifo_size = acp63_sdw0_dma_reg[stream_id].reg_fifo_size;

		reg_ring_buf_size = acp63_sdw0_dma_reg[stream_id].reg_ring_buf_size;

		reg_ring_buf_addr = acp63_sdw0_dma_reg[stream_id].reg_ring_buf_addr;

		break;

	case ACP_SDW1:

		reg_dma_size = sdw1_dma_ring_buf_reg[stream_id].reg_dma_size;

		reg_fifo_addr =	sdw1_dma_ring_buf_reg[stream_id].reg_fifo_addr;

		reg_fifo_size = sdw1_dma_ring_buf_reg[stream_id].reg_fifo_size;

		reg_ring_buf_size = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_size;

		reg_ring_buf_addr = sdw1_dma_ring_buf_reg[stream_id].reg_ring_buf_addr;

		reg_dma_size = acp63_sdw1_dma_reg[stream_id].reg_dma_size;

		reg_fifo_addr =	acp63_sdw1_dma_reg[stream_id].reg_fifo_addr;

		reg_fifo_size = acp63_sdw1_dma_reg[stream_id].reg_fifo_size;

		reg_ring_buf_size = acp63_sdw1_dma_reg[stream_id].reg_ring_buf_size;

		reg_ring_buf_addr = acp63_sdw1_dma_reg[stream_id].reg_ring_buf_addr;

		break;

	default:

		return -EINVAL;
@@ -267,19 +267,19 @@ static int acp63_sdw_dma_hw_params(struct snd_soc_component *component, 
	stream_id = stream->stream_id;

	switch (stream->instance) {

	case ACP_SDW0:

		sdw_data->sdw0_dma_stream[stream_id] = substream;

		water_mark_size_reg = sdw0_dma_ring_buf_reg[stream_id].water_mark_size_reg;

		sdw_data->acp63_sdw0_dma_stream[stream_id] = substream;

		water_mark_size_reg = acp63_sdw0_dma_reg[stream_id].water_mark_size_reg;

		acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL;

		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)

			irq_mask = BIT(SDW0_DMA_TX_IRQ_MASK(stream_id));

			irq_mask = BIT(ACP63_SDW0_DMA_TX_IRQ_MASK(stream_id));

		else

			irq_mask = BIT(SDW0_DMA_RX_IRQ_MASK(stream_id));

			irq_mask = BIT(ACP63_SDW0_DMA_RX_IRQ_MASK(stream_id));

		break;

	case ACP_SDW1:

		sdw_data->sdw1_dma_stream[stream_id] = substream;

		sdw_data->acp63_sdw1_dma_stream[stream_id] = substream;

		acp_ext_intr_cntl_reg = ACP_EXTERNAL_INTR_CNTL1;

		water_mark_size_reg = sdw1_dma_ring_buf_reg[stream_id].water_mark_size_reg;

		irq_mask = BIT(SDW1_DMA_IRQ_MASK(stream_id));

		water_mark_size_reg = acp63_sdw1_dma_reg[stream_id].water_mark_size_reg;

		irq_mask = BIT(ACP63_SDW1_DMA_IRQ_MASK(stream_id));

		break;

	default:

		return -EINVAL;
@@ -310,12 +310,12 @@ static u64 acp63_sdw_get_byte_count(struct acp_sdw_dma_stream *stream, void __io 
	byte_count.bytescount = 0;

	switch (stream->instance) {

	case ACP_SDW0:

		pos_low_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_low_reg;

		pos_high_reg = sdw0_dma_ring_buf_reg[stream->stream_id].pos_high_reg;

		pos_low_reg = acp63_sdw0_dma_reg[stream->stream_id].pos_low_reg;

		pos_high_reg = acp63_sdw0_dma_reg[stream->stream_id].pos_high_reg;

		break;

	case ACP_SDW1:

		pos_low_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_low_reg;

		pos_high_reg = sdw1_dma_ring_buf_reg[stream->stream_id].pos_high_reg;

		pos_low_reg = acp63_sdw1_dma_reg[stream->stream_id].pos_low_reg;

		pos_high_reg = acp63_sdw1_dma_reg[stream->stream_id].pos_high_reg;

		break;

	default:

		goto POINTER_RETURN_BYTES;
@@ -369,10 +369,10 @@ static int acp63_sdw_dma_close(struct snd_soc_component *component, 
		return -EINVAL;

	switch (stream->instance) {

	case ACP_SDW0:

		sdw_data->sdw0_dma_stream[stream->stream_id] = NULL;

		sdw_data->acp63_sdw0_dma_stream[stream->stream_id] = NULL;

		break;

	case ACP_SDW1:

		sdw_data->sdw1_dma_stream[stream->stream_id] = NULL;

		sdw_data->acp63_sdw1_dma_stream[stream->stream_id] = NULL;

		break;

	default:

		return -EINVAL;
@@ -395,10 +395,10 @@ static int acp63_sdw_dma_enable(struct snd_pcm_substream *substream, 
	stream_id = stream->stream_id;

	switch (stream->instance) {

	case ACP_SDW0:

		sdw_dma_en_reg = sdw0_dma_enable_reg[stream_id];

		sdw_dma_en_reg = acp63_sdw0_dma_enable_reg[stream_id];

		break;

	case ACP_SDW1:

		sdw_dma_en_reg = sdw1_dma_enable_reg[stream_id];

		sdw_dma_en_reg = acp63_sdw1_dma_enable_reg[stream_id];

		break;

	default:

		return -EINVAL;
@@ -512,13 +512,11 @@ static int acp_restore_sdw_dma_config(struct sdw_dma_dev_data *sdw_data) 


		for (index = 0; index < stream_count; index++) {

			if (instance == ACP_SDW0) {

				substream = sdw_data->sdw0_dma_stream[index];

				water_mark_size_reg =

						sdw0_dma_ring_buf_reg[index].water_mark_size_reg;

				substream = sdw_data->acp63_sdw0_dma_stream[index];

				water_mark_size_reg = acp63_sdw0_dma_reg[index].water_mark_size_reg;

			} else {

				substream = sdw_data->sdw1_dma_stream[index];

				water_mark_size_reg =

						sdw1_dma_ring_buf_reg[index].water_mark_size_reg;

				substream = sdw_data->acp63_sdw1_dma_stream[index];

				water_mark_size_reg = acp63_sdw1_dma_reg[index].water_mark_size_reg;

			}



			if (substream && substream->runtime) {