Commit e329b762 authored by Conor Dooley's avatar Conor Dooley Committed by Bjorn Helgaas
Browse files

dt-bindings: PCI: microchip,pcie-host: Add reg for Root Port 2 

The PCI host controller on PolarFire SoC has multiple Root Port instances,
each with their own bridge and ctrl address spaces. The original binding
has an "apb" register region, and it is expected to be set to the base
address of the Root Complex register space. Some defines in the Linux
driver were used to compute the addresses of the bridge and ctrl address
ranges corresponding to Root Port instance 1.  Some customers want to use
Root Port instance 2 however, which requires changing the defines in the
driver, which is clearly not a portable solution.

Remove this "apb" register region from the binding and add "bridge" &
"ctrl" regions instead, that will directly communicate the address of these
regions for a specific Root Port.

Fixes: 6ee6c89a ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
Link: https://lore.kernel.org/r/20241107-barcode-whinny-b1a4e8834b4f@spud


Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
[bhelgaas: Capitalize PCIe spec terms]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarDaire McNamara <daire.mcnamara@microchip.com>
parent 9852d85e

Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml

+9 −2
Original line number Diff line number Diff line
@@ -17,6 +17,12 @@ properties: 
  compatible:

    const: microchip,pcie-host-1.0 # PolarFire



  reg:

    minItems: 3



  reg-names:

    minItems: 3



  clocks:

    description:

      Fabric Interface Controllers, FICs, are the interface between the FPGA
@@ -62,8 +68,9 @@ examples: 
            pcie0: pcie@2030000000 {

                    compatible = "microchip,pcie-host-1.0";

                    reg = <0x0 0x70000000 0x0 0x08000000>,

                          <0x0 0x43000000 0x0 0x00010000>;

                    reg-names = "cfg", "apb";

                          <0x0 0x43008000 0x0 0x00002000>,

                          <0x0 0x4300a000 0x0 0x00002000>;

                    reg-names = "cfg", "bridge", "ctrl";

                    device_type = "pci";

                    #address-cells = <3>;

                    #size-cells = <2>;

Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml

+10 −4
Original line number Diff line number Diff line
@@ -18,12 +18,18 @@ allOf: 


properties:

  reg:

    maxItems: 2

    maxItems: 3

    minItems: 2



  reg-names:

    items:

    oneOf:

      - items:

          - const: cfg

          - const: apb

      - items:

          - const: cfg

          - const: bridge

          - const: ctrl



  interrupts:

    minItems: 1

Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml

+7 −0
Original line number Diff line number Diff line
@@ -16,6 +16,13 @@ properties: 
  compatible:

    const: starfive,jh7110-pcie





  reg:

    maxItems: 2



  reg-names:

    maxItems: 2



  clocks:

    items:

      - description: NOC bus clock