Commit e34a7238 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/hisilicon/kirin: Fix 64bit divisions 



Use the appropriate 64bit division helpers to make the code
build on 32bit architectures.

Cc: Xinliang Liu <xinliang.liu@linaro.org>
Cc: Tian Tao <tiantao6@hisilicon.com>
Cc: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Yongqin Liu <yongqin.liu@linaro.org>
Cc: John Stultz <jstultz@google.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240408170426.9285-10-ville.syrjala@linux.intel.com


Acked-by: default avatarJohn Stultz <jstultz@google.com>
parent 4a7fe057

drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c

+5 −6
Original line number Diff line number Diff line
@@ -157,8 +157,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) 
			q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);



		temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;

		m_n_int = temp / (u64)1000000000;

		m_n = (temp % (u64)1000000000) / (u64)100000000;

		m_n_int = div64_u64_rem(temp, 1000000000, &temp);

		m_n = div_u64(temp, 100000000);



		if (m_n_int % 2 == 0) {

			if (m_n * 6 >= 50) {
@@ -229,9 +229,8 @@ static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) 
			phy->pll_fbd_div5f = 1;

		}



		f_kHz = (u64)1000000000 * (u64)m_pll /

			((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);



		f_kHz = div64_u64((u64)1000000000 * (u64)m_pll,

				  (u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);

		if (f_kHz >= req_kHz)

			break;
@@ -490,7 +489,7 @@ static void dsi_set_mode_timing(void __iomem *base, 
	hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;

	hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;

	tmp = (u64)htot * (u64)lane_byte_clk_kHz;

	hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);

	hline_time = DIV_ROUND_UP_ULL(tmp, pixel_clk_kHz);



	/* all specified in byte-lane clocks */

	writel(hsa_time, base + VID_HSA_TIME);