Commit e34b9430 authored by Praveen Teja Kundanala's avatar Praveen Teja Kundanala Committed by Greg Kroah-Hartman
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firmware: xilinx: Add ZynqMP efuse access API 



Add zynqmp_pm_efuse_access API in the ZynqMP
firmware for read/write access of efuse memory.

Signed-off-by: default avatarPraveen Teja Kundanala <praveen.teja.kundanala@amd.com>
Acked-by: default avatarMichal Simek <michal.simek@amd.com>
Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20240224114516.86365-6-srinivas.kandagatla@linaro.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d28c853b

drivers/firmware/xilinx/zynqmp.c

+25 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * Xilinx Zynq MPSoC Firmware layer

 *

 *  Copyright (C) 2014-2022 Xilinx, Inc.

 *  Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.

 *

 *  Michal Simek <michal.simek@amd.com>

 *  Davorin Mista <davorin.mista@aggios.com>
@@ -1384,6 +1385,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out) 
}

EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);



/**

 * zynqmp_pm_efuse_access - Provides access to efuse memory.

 * @address:	Address of the efuse params structure

 * @out:		Returned output value

 *

 * Return:	Returns status, either success or error code.

 */

int zynqmp_pm_efuse_access(const u64 address, u32 *out)

{

	u32 ret_payload[PAYLOAD_ARG_CNT];

	int ret;



	if (!out)

		return -EINVAL;



	ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, ret_payload, 2,

				  upper_32_bits(address),

				  lower_32_bits(address));

	*out = ret_payload[1];



	return ret;

}

EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access);



/**

 * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash

 * @address:	Address of the data/ Address of output buffer where

include/linux/firmware/xlnx-zynqmp.h

+8 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * Xilinx Zynq MPSoC Firmware layer

 *

 *  Copyright (C) 2014-2021 Xilinx

 *  Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.

 *

 *  Michal Simek <michal.simek@amd.com>

 *  Davorin Mista <davorin.mista@aggios.com>
@@ -171,6 +172,7 @@ enum pm_api_id { 
	PM_CLOCK_GETPARENT = 44,

	PM_FPGA_READ = 46,

	PM_SECURE_AES = 47,

	PM_EFUSE_ACCESS = 53,

	PM_FEATURE_CHECK = 63,

};
@@ -562,6 +564,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, 
			      const u32 qos,

			      const enum zynqmp_pm_request_ack ack);

int zynqmp_pm_aes_engine(const u64 address, u32 *out);

int zynqmp_pm_efuse_access(const u64 address, u32 *out);

int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);

int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);

int zynqmp_pm_fpga_get_status(u32 *value);
@@ -749,6 +752,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) 
	return -ENODEV;

}



static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out)

{

	return -ENODEV;

}



static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,

				     const u32 flags)

{