Commit e367e3c7 authored by LeoLiuoc's avatar LeoLiuoc Committed by Bjorn Helgaas
Browse files

PCI: Add ACS quirk for more Zhaoxin Root Ports 

Add more Root Port Device IDs to pci_quirk_zhaoxin_pcie_ports_acs() for
some new Zhaoxin platforms.

Fixes: 299bd044 ("PCI: Add ACS quirk for Zhaoxin Root/Downstream Ports")
Link: https://lore.kernel.org/r/20231211091543.735903-1-LeoLiu-oc@zhaoxin.com


Signed-off-by: default avatarLeoLiuoc <LeoLiu-oc@zhaoxin.com>
[bhelgaas: update subject, drop changelog, add Fixes, add stable tag, fix
whitespace, wrap code comment]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Cc: <stable@vger.kernel.org>	# 5.7
parent b85ea95d

drivers/pci/quirks.c

+6 −2
Original line number Diff line number Diff line
@@ -4706,10 +4706,14 @@ static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 
	     (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))

		return -ENOTTY;



	/*

	 * Future Zhaoxin Root Ports and Switch Downstream Ports will

	 * implement ACS capability in accordance with the PCIe Spec.

	 */

	switch (dev->device) {

	case 0x0710 ... 0x071e:

	case 0x0721:

	case 0x0723 ... 0x0732:

	case 0x0723 ... 0x0752:

		return pci_acs_ctrl_enabled(acs_flags,

			PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);

	}