Unverified Commit e36f6de6 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'amlogic-fixes-for-v6.15' of...

Merge tag 'amlogic-fixes-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/fixes

Amlogic Fixes for v6.15:
- fix reference to unknown/untested PWM clock on ARM/ARM64 boards
- fix missing clkc_audio node on dreambox ARM64 DT

* tag 'amlogic-fixes-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: amlogic: dreambox: fix missing clkc_audio node
  arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock
  arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock
  ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock
  ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock

Link: https://lore.kernel.org/r/e9c520a1-b986-49e1-b9b1-67511c187716@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 81b7cf86 0f675785
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+3 −3
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ analog_top: analog-top@81a8 {
	pwm_ef: pwm@86c0 {
		compatible = "amlogic,meson8-pwm-v2";
		clocks = <&xtal>,
			 <>, /* unknown/untested, the datasheet calls it "Video PLL" */
			 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
			 <&clkc CLKID_FCLK_DIV4>,
			 <&clkc CLKID_FCLK_DIV3>;
		reg = <0x86c0 0x10>;
@@ -705,7 +705,7 @@ timer@600 {
&pwm_ab {
	compatible = "amlogic,meson8-pwm-v2";
	clocks = <&xtal>,
		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>;
};
@@ -713,7 +713,7 @@ &pwm_ab {
&pwm_cd {
	compatible = "amlogic,meson8-pwm-v2";
	clocks = <&xtal>,
		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>;
};
+3 −3
Original line number Diff line number Diff line
@@ -406,7 +406,7 @@ pwm_ef: pwm@86c0 {
		compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
		reg = <0x86c0 0x10>;
		clocks = <&xtal>,
			 <>, /* unknown/untested, the datasheet calls it "Video PLL" */
			 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
			 <&clkc CLKID_FCLK_DIV4>,
			 <&clkc CLKID_FCLK_DIV3>;
		#pwm-cells = <3>;
@@ -680,7 +680,7 @@ timer@600 {
&pwm_ab {
	compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
	clocks = <&xtal>,
		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>;
};
@@ -688,7 +688,7 @@ &pwm_ab {
&pwm_cd {
	compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
	clocks = <&xtal>,
		 <>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <0>, /* unknown/untested, the datasheet calls it "Video PLL" */
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>;
};
+3 −3
Original line number Diff line number Diff line
@@ -2313,7 +2313,7 @@ pwm_ef: pwm@19000 {
					     "amlogic,meson8-pwm-v2";
				reg = <0x0 0x19000 0x0 0x20>;
				clocks = <&xtal>,
					 <>, /* unknown/untested, the datasheet calls it "vid_pll" */
					 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
					 <&clkc CLKID_FCLK_DIV4>,
					 <&clkc CLKID_FCLK_DIV3>;
				#pwm-cells = <3>;
@@ -2325,7 +2325,7 @@ pwm_cd: pwm@1a000 {
					     "amlogic,meson8-pwm-v2";
				reg = <0x0 0x1a000 0x0 0x20>;
				clocks = <&xtal>,
					 <>, /* unknown/untested, the datasheet calls it "vid_pll" */
					 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
					 <&clkc CLKID_FCLK_DIV4>,
					 <&clkc CLKID_FCLK_DIV3>;
				#pwm-cells = <3>;
@@ -2337,7 +2337,7 @@ pwm_ab: pwm@1b000 {
					     "amlogic,meson8-pwm-v2";
				reg = <0x0 0x1b000 0x0 0x20>;
				clocks = <&xtal>,
					 <>, /* unknown/untested, the datasheet calls it "vid_pll" */
					 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
					 <&clkc CLKID_FCLK_DIV4>,
					 <&clkc CLKID_FCLK_DIV3>;
				#pwm-cells = <3>;
+4 −0
Original line number Diff line number Diff line
@@ -116,6 +116,10 @@ &arb {
	status = "okay";
};

&clkc_audio {
	status = "okay";
};

&frddr_a {
	status = "okay";
};
+3 −3
Original line number Diff line number Diff line
@@ -741,7 +741,7 @@ mux {

&pwm_ab {
	clocks = <&xtal>,
		 <>, /* unknown/untested, the datasheet calls it "vid_pll" */
		 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>;
};
@@ -752,14 +752,14 @@ &pwm_AO_ab {

&pwm_cd {
	clocks = <&xtal>,
		 <>, /* unknown/untested, the datasheet calls it "vid_pll" */
		 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>;
};

&pwm_ef {
	clocks = <&xtal>,
		 <>, /* unknown/untested, the datasheet calls it "vid_pll" */
		 <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>;
};
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