Commit e37546ad authored by Jiawen Wu's avatar Jiawen Wu Committed by Paolo Abeni
Browse files

net: wangxun: revert the adjustment of the IRQ vector sequence 



Due to hardware limitations of NGBE, queue IRQs can only be requested
on vector 0 to 7. When the number of queues is set to the maximum 8,
the PCI IRQ vectors are allocated from 0 to 8. The vector 0 is used by
MISC interrupt, and althrough the vector 8 is used by queue interrupt,
it is unable to receive packets. This will cause some packets to be
dropped when RSS is enabled and they are assigned to queue 8.

So revert the adjustment of the MISC IRQ location, to make it be the
last one in IRQ vectors.

Fixes: 937d46ec ("net: wangxun: add ethtool_ops for channel number")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: default avatarLarysa Zaremba <larysa.zaremba@intel.com>
Link: https://patch.msgid.link/20250701063030.59340-3-jiawenwu@trustnetic.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent cc9f7f65

drivers/net/ethernet/wangxun/libwx/wx_lib.c

+8 −9
Original line number Diff line number Diff line
@@ -1747,7 +1747,7 @@ static void wx_set_num_queues(struct wx *wx) 
 */

static int wx_acquire_msix_vectors(struct wx *wx)

{

	struct irq_affinity affd = { .pre_vectors = 1 };

	struct irq_affinity affd = { .post_vectors = 1 };

	int nvecs, i;



	/* We start by asking for one vector per queue pair */
@@ -1784,16 +1784,17 @@ static int wx_acquire_msix_vectors(struct wx *wx) 
		return nvecs;

	}



	wx->msix_entry->entry = 0;

	wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0);

	nvecs -= 1;

	for (i = 0; i < nvecs; i++) {

		wx->msix_q_entries[i].entry = i;

		wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i + 1);

		wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i);

	}



	wx->num_q_vectors = nvecs;



	wx->msix_entry->entry = nvecs;

	wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs);



	return 0;

}
@@ -2300,8 +2301,6 @@ static void wx_set_ivar(struct wx *wx, s8 direction, 
		wr32(wx, WX_PX_MISC_IVAR, ivar);

	} else {

		/* tx or rx causes */

		if (!(wx->mac.type == wx_mac_em && wx->num_vfs == 7))

			msix_vector += 1; /* offset for queue vectors */

		msix_vector |= WX_PX_IVAR_ALLOC_VAL;

		index = ((16 * (queue & 1)) + (8 * direction));

		ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
@@ -2340,7 +2339,7 @@ void wx_write_eitr(struct wx_q_vector *q_vector) 


	itr_reg |= WX_PX_ITR_CNT_WDIS;



	wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg);

	wr32(wx, WX_PX_ITR(v_idx), itr_reg);

}



/**
@@ -2393,9 +2392,9 @@ void wx_configure_vectors(struct wx *wx) 
		wx_write_eitr(q_vector);

	}



	wx_set_ivar(wx, -1, 0, 0);

	wx_set_ivar(wx, -1, 0, v_idx);

	if (pdev->msix_enabled)

		wr32(wx, WX_PX_ITR(0), 1950);

		wr32(wx, WX_PX_ITR(v_idx), 1950);

}

EXPORT_SYMBOL(wx_configure_vectors);

drivers/net/ethernet/wangxun/libwx/wx_type.h

+1 −1
Original line number Diff line number Diff line
@@ -1343,7 +1343,7 @@ struct wx { 
};



#define WX_INTR_ALL (~0ULL)

#define WX_INTR_Q(i) BIT((i) + 1)

#define WX_INTR_Q(i) BIT((i))



/* register operations */

#define wr32(a, reg, value)	writel((value), ((a)->hw_addr + (reg)))

drivers/net/ethernet/wangxun/ngbe/ngbe_main.c

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static void ngbe_irq_enable(struct wx *wx, bool queues) 
	if (queues)

		wx_intr_enable(wx, NGBE_INTR_ALL);

	else

		wx_intr_enable(wx, NGBE_INTR_MISC);

		wx_intr_enable(wx, NGBE_INTR_MISC(wx));

}



/**

drivers/net/ethernet/wangxun/ngbe/ngbe_type.h

+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ 
#define NGBE_PX_MISC_IC_TIMESYNC		BIT(11) /* time sync */



#define NGBE_INTR_ALL				0x1FF

#define NGBE_INTR_MISC				BIT(0)

#define NGBE_INTR_MISC(A)			BIT((A)->num_q_vectors)



#define NGBE_PHY_CONFIG(reg_offset)		(0x14000 + ((reg_offset) * 4))

#define NGBE_CFG_LAN_SPEED			0x14440

drivers/net/ethernet/wangxun/txgbe/txgbe_irq.c

+3 −3
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ void txgbe_irq_enable(struct wx *wx, bool queues) 
	wr32(wx, WX_PX_MISC_IEN, misc_ien);



	/* unmask interrupt */

	wx_intr_enable(wx, TXGBE_INTR_MISC);

	wx_intr_enable(wx, TXGBE_INTR_MISC(wx));

	if (queues)

		wx_intr_enable(wx, TXGBE_INTR_QALL(wx));

}
@@ -131,7 +131,7 @@ static irqreturn_t txgbe_misc_irq_handle(int irq, void *data) 
		txgbe->eicr = eicr;

		if (eicr & TXGBE_PX_MISC_IC_VF_MBOX) {

			wx_msg_task(txgbe->wx);

			wx_intr_enable(wx, TXGBE_INTR_MISC);

			wx_intr_enable(wx, TXGBE_INTR_MISC(wx));

		}

		return IRQ_WAKE_THREAD;

	}
@@ -183,7 +183,7 @@ static irqreturn_t txgbe_misc_irq_thread_fn(int irq, void *data) 
		nhandled++;

	}



	wx_intr_enable(wx, TXGBE_INTR_MISC);

	wx_intr_enable(wx, TXGBE_INTR_MISC(wx));

	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);

}