Commit e37a95d0 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Biju Das
Browse files

drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range 



The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.

Co-developed-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-2-prabhakar.mahadev-lad.rj@bp.renesas.com
parent 660942f2

drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c

+3 −0
Original line number Diff line number Diff line
@@ -612,6 +612,9 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 
	if (mode->clock > 148500)

		return MODE_CLOCK_HIGH;



	if (mode->clock < 5803)

		return MODE_CLOCK_LOW;



	return MODE_OK;

}