Commit e37fb0f8 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Use feature bits data structure 



Feature bits are not necessarily restricted to 64-bits. Use
smu_feature_bits data structure to represent feature mask for checking
DPM status.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 97a96893

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+17 −0
Original line number Diff line number Diff line
@@ -477,6 +477,23 @@ struct smu_feature_bits { 
	DECLARE_BITMAP(bits, SMU_FEATURE_MAX);

};



/*

 * Helpers for initializing smu_feature_bits statically.

 * Use SMU_FEATURE_BIT_INIT() which automatically handles array indexing:

 *   static const struct smu_feature_bits example = {

 *       .bits = {

 *           SMU_FEATURE_BIT_INIT(5),

 *           SMU_FEATURE_BIT_INIT(10),

 *           SMU_FEATURE_BIT_INIT(65),

 *           SMU_FEATURE_BIT_INIT(100)

 *       }

 *   };

 */

#define SMU_FEATURE_BITS_ELEM(bit) ((bit) / BITS_PER_LONG)

#define SMU_FEATURE_BITS_POS(bit) ((bit) % BITS_PER_LONG)

#define SMU_FEATURE_BIT_INIT(bit) \

	[SMU_FEATURE_BITS_ELEM(bit)] = (1UL << SMU_FEATURE_BITS_POS(bit))



enum smu_feature_list {

	SMU_FEATURE_LIST_SUPPORTED,

	SMU_FEATURE_LIST_ALLOWED,

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+12 −9
Original line number Diff line number Diff line
@@ -65,14 +65,15 @@ 
#define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000

#define SMU_FEATURES_HIGH_SHIFT      32



#define SMC_DPM_FEATURE ( \

	FEATURE_DPM_PREFETCHER_MASK | \

	FEATURE_DPM_GFXCLK_MASK | \

	FEATURE_DPM_UCLK_MASK | \

	FEATURE_DPM_SOCCLK_MASK | \

	FEATURE_DPM_MP0CLK_MASK | \

	FEATURE_DPM_FCLK_MASK | \

	FEATURE_DPM_XGMI_MASK)

static const struct smu_feature_bits arcturus_dpm_features = {

	.bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),

		  SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),

		  SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),

		  SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),

		  SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT),

		  SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),

		  SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT) }

};



#define smnPCIE_ESM_CTRL			0x111003D0
@@ -1527,12 +1528,14 @@ static bool arcturus_is_dpm_running(struct smu_context *smu) 
{

	int ret = 0;

	uint64_t feature_enabled;

	uint32_t feature_mask[2];



	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);

	if (ret)

		return false;



	return !!(feature_enabled & SMC_DPM_FEATURE);

	smu_feature_bits_to_arr32(&arcturus_dpm_features, feature_mask, 64);

	return !!(feature_enabled & *(uint64_t *)feature_mask);

}



static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

+10 −6
Original line number Diff line number Diff line
@@ -60,11 +60,13 @@ static struct gfx_user_settings { 


static uint32_t cyan_skillfish_sclk_default;



#define FEATURE_MASK(feature) (1ULL << feature)

#define SMC_DPM_FEATURE ( \

	FEATURE_MASK(FEATURE_FCLK_DPM_BIT)	|	\

	FEATURE_MASK(FEATURE_SOC_DPM_BIT)	|	\

	FEATURE_MASK(FEATURE_GFX_DPM_BIT))

static const struct smu_feature_bits cyan_skillfish_dpm_features = {

	.bits = {

		SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_SOC_DPM_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT)

	}

};



static struct cmn2asic_msg_mapping cyan_skillfish_message_map[SMU_MSG_MAX_COUNT] = {

	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,			0),
@@ -362,6 +364,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) 
	struct amdgpu_device *adev = smu->adev;

	int ret = 0;

	uint64_t feature_enabled;

	uint32_t feature_mask[2];



	/* we need to re-init after suspend so return false */

	if (adev->in_suspend)
@@ -378,7 +381,8 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) 
		cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK,

			&cyan_skillfish_sclk_default);



	return !!(feature_enabled & SMC_DPM_FEATURE);

	smu_feature_bits_to_arr32(&cyan_skillfish_dpm_features, feature_mask, 64);

	return !!(feature_enabled & *(uint64_t *)feature_mask);

}



static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+15 −11
Original line number Diff line number Diff line
@@ -58,16 +58,18 @@ 
#undef pr_info

#undef pr_debug



#define FEATURE_MASK(feature) (1ULL << feature)

#define SMC_DPM_FEATURE ( \

	FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \

	FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_UCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_LINK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))

static const struct smu_feature_bits navi10_dpm_features = {

	.bits = {

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFX_PACE_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT)

	}

};



#define SMU_11_0_GFX_BUSY_THRESHOLD 15
@@ -1620,12 +1622,14 @@ static bool navi10_is_dpm_running(struct smu_context *smu) 
{

	int ret = 0;

	uint64_t feature_enabled;

	uint32_t feature_mask[2];



	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);

	if (ret)

		return false;



	return !!(feature_enabled & SMC_DPM_FEATURE);

	smu_feature_bits_to_arr32(&navi10_dpm_features, feature_mask, 64);

	return !!(feature_enabled & *(uint64_t *)feature_mask);

}



static int navi10_get_fan_speed_rpm(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+15 −11
Original line number Diff line number Diff line
@@ -60,16 +60,18 @@ 
#undef pr_info

#undef pr_debug



#define FEATURE_MASK(feature) (1ULL << feature)

#define SMC_DPM_FEATURE ( \

	FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \

	FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \

	FEATURE_MASK(FEATURE_DPM_UCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \

	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \

	FEATURE_MASK(FEATURE_DPM_FCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))

static const struct smu_feature_bits sienna_cichlid_dpm_features = {

	.bits = {

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT),

		SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT)

	}

};



#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
@@ -1535,12 +1537,14 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) 
{

	int ret = 0;

	uint64_t feature_enabled;

	uint32_t feature_mask[2];



	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);

	if (ret)

		return false;



	return !!(feature_enabled & SMC_DPM_FEATURE);

	smu_feature_bits_to_arr32(&sienna_cichlid_dpm_features, feature_mask, 64);

	return !!(feature_enabled & *(uint64_t *)feature_mask);

}



static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,