Commit e3995e08 authored by Wayne Boyer's avatar Wayne Boyer Committed by Matt Roper
Browse files

drm/i915/pvc: Implement recommended caching policy 



As per the performance tuning guide, set the HOSTCACHEEN bit to
implement the recommended caching policy on PVC.

Signed-off-by: default avatarWayne Boyer <wayne.boyer@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221130170723.2460014-1-wayne.boyer@intel.com
parent 9bbba066

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -972,6 +972,7 @@ 
#define   GEN7_L3AGDIS				(1 << 19)



#define XEHPC_LNCFMISCCFGREG0			_MMIO(0xb01c)

#define   XEHPC_HOSTCACHEEN			REG_BIT(1)

#define   XEHPC_OVRLSCCC			REG_BIT(0)



#define GEN7_L3CNTLREG2				_MMIO(0xb020)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+1 −0
Original line number Diff line number Diff line
@@ -2906,6 +2906,7 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915, 
	if (IS_PONTEVECCHIO(i915)) {

		wa_write(wal, XEHPC_L3SCRUB,

			 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);

		wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);

	}



	if (IS_DG2(i915)) {