Commit e3a52b67 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

x86/fpu: Clarify FPU context cacheline alignment 



Suggested-by: default avatarPeter Zijlstra <peterz@infradead.org>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Chang S. Bae <chang.seok.bae@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Link: https://lore.kernel.org/r/Z_ejggklB5-IWB5W@gmail.com
parent 8b2a7a72

arch/x86/kernel/fpu/core.c

+2 −1
Original line number Diff line number Diff line
@@ -607,7 +607,8 @@ int fpu_clone(struct task_struct *dst, unsigned long clone_flags, bool minimal, 
	 * We allocate the new FPU structure right after the end of the task struct.

	 * task allocation size already took this into account.

	 *

	 * This is safe because task_struct size is a multiple of cacheline size.

	 * This is safe because task_struct size is a multiple of cacheline size,

	 * thus x86_task_fpu() will always be cacheline aligned as well.

	 */

	struct fpu *dst_fpu = (void *)dst + sizeof(*dst);