Commit e3b8d8cc authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdgpu: Fix SHMEM alignment mode for GFX 12.1.0 



Alignment mode in SHMEM config register is only a single bit
value on GFX 12.1.0 instead of 2 bits in previous asics.
Add a new enum and use the correct value of SHMEM alignment mode
when programming the SHMEM config register.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3849efdc

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

+2 −1
Original line number Diff line number Diff line
@@ -52,9 +52,10 @@ 
MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin");

MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin");



#define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0	0x00000001

#define DEFAULT_SH_MEM_CONFIG \

	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \

	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))



static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 


#include "kfd_device_queue_manager.h"

#include "gc/gc_12_1_0_sh_mask.h"

#include "soc24_enum.h"

#include "soc_v1_0_enum.h"



static int update_qpd_v12_1(struct device_queue_manager *dqm,

			 struct qcm_process_device *qpd);

drivers/gpu/drm/amd/include/soc_v1_0_enum.h

+5 −0
Original line number Diff line number Diff line
@@ -30,4 +30,9 @@ typedef enum MTYPE { 
	MTYPE_UC			= 0x00000003,

} MTYPE;



typedef enum SH_MEM_ALIGNMENT_MODE {

	SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,

	SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000001,

} SH_MEM_ALIGNMENT_MODE;



#endif