Commit e3dfcf48 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Nishanth Menon
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arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable ACSPCIE0 output for PCIe1 



The PCIe reference clock required by the PCIe Endpoints connected to the
PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM
and J742S2-EVM is driven by the ACSPCIE0 module. Add the device-tree
support for enabling the same.

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: default avatarUdit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250422123218.3788223-3-s-vadapalli@ti.com


Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent 9bfebd87

arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -5,6 +5,9 @@ 
 * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458

 * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001

 */



#include <dt-bindings/phy/phy-cadence.h>



/ {

	chosen {

		stdout-path = "serial2:115200n8";
@@ -1407,10 +1410,13 @@ &main_mcan4 { 


&pcie1_rc {

	status = "okay";

	clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;

	clock-names = "fck", "pcie_refclk";

	num-lanes = <2>;

	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;

	phys = <&serdes0_pcie1_link>;

	phy-names = "pcie-phy";

	ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>;

};



&serdes1 {