Commit e3f42c43 authored by Ignacio Encinas's avatar Ignacio Encinas Committed by Yury Norov
Browse files

riscv: fix test_and_{set,clear}_bit ordering documentation 



test_and_{set,clear}_bit are fully ordered as specified in
Documentation/atomic_bitops.txt. Fix incorrect comment stating otherwise.

Note that the implementation is correct since commit
9347ce54 ("RISC-V: __test_and_op_bit_ord should be strongly ordered")
was introduced.

Signed-off-by: default avatarIgnacio Encinas <ignacio@iencinas.com>
Signed-off-by: default avatarYury Norov <yury.norov@gmail.com>
parent 0312e94a

arch/riscv/include/asm/bitops.h

+2 −2
Original line number Diff line number Diff line
@@ -226,7 +226,7 @@ static __always_inline int variable_fls(unsigned int x) 
 * @nr: Bit to set

 * @addr: Address to count from

 *

 * This operation may be reordered on other architectures than x86.

 * This is an atomic fully-ordered operation (implied full memory barrier).

 */

static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long *addr)

{
@@ -238,7 +238,7 @@ static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long 
 * @nr: Bit to clear

 * @addr: Address to count from

 *

 * This operation can be reordered on other architectures other than x86.

 * This is an atomic fully-ordered operation (implied full memory barrier).

 */

static __always_inline int arch_test_and_clear_bit(int nr, volatile unsigned long *addr)

{