Commit e3f79bdb authored by Frank Li's avatar Frank Li Committed by Shawn Guo
Browse files

arm64: dts: imx8x: add cm41 subsystem dtsi 



Add cm41 subsystem dtsi for iMX8X chips.

Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d032d7fc

arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi

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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2024 NXP

 *	Dong Aisheng <aisheng.dong@nxp.com>

 */



#include <dt-bindings/firmware/imx/rsrc.h>

#include <dt-bindings/clock/imx8-lpcg.h>



cm41_ipg_clk: clock-cm41-ipg {

	compatible = "fixed-clock";

	#clock-cells = <0>;

	clock-frequency = <132000000>;

	clock-output-names = "cm41_ipg_clk";

};



cm41_subsys: bus@38000000 {

	compatible = "simple-bus";

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0x38000000 0x0 0x38000000 0x4000000>;

	interrupt-parent = <&cm41_intmux>;



	cm41_i2c: i2c@3b230000 {

		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

		reg = <0x3b230000 0x1000>;

		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cm41_i2c_lpcg IMX_LPCG_CLK_0>,

			 <&cm41_i2c_lpcg IMX_LPCG_CLK_4>;

		clock-names = "per", "ipg";

		assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <24000000>;

		power-domains = <&pd IMX_SC_R_M4_1_I2C>;

		status = "disabled";

	};



	cm41_intmux: intmux@3b400000 {

		compatible = "fsl,imx-intmux";

		reg = <0x3b400000 0x1000>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <2>;

		clocks = <&cm41_ipg_clk>;

		clock-names = "ipg";

		power-domains = <&pd IMX_SC_R_M4_1_INTMUX>;

		status = "disabled";

	};



	cm41_i2c_lpcg: clock-controller@3b630000 {

		compatible = "fsl,imx8qxp-lpcg";

		reg = <0x3b630000 0x1000>;

		#clock-cells = <1>;

		clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>,

			 <&cm41_ipg_clk>;

		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;

		clock-output-names = "cm41_lpcg_i2c_clk",

				     "cm41_lpcg_i2c_ipg_clk";

		power-domains = <&pd IMX_SC_R_M4_1_I2C>;

	};

};

arch/arm64/boot/dts/freescale/imx8qm.dtsi

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@@ -546,6 +546,7 @@ clk_spdif1_rx: clock-spdif1-rx { 
	};



	/* sorted in register address */

	#include "imx8-ss-cm41.dtsi"

	#include "imx8-ss-audio.dtsi"

	#include "imx8-ss-vpu.dtsi"

	#include "imx8-ss-img.dtsi"