Commit e43b186d authored by Tommaso Merciai's avatar Tommaso Merciai Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g047: Add clock and reset entries for USB2 



Add clock and reset entries for USB2.

Signed-off-by: default avatarTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251001212709.579080-10-tommaso.merciai.xr@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent daa5a9bc

drivers/clk/renesas/r9a09g047-cpg.c

+17 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,

	LAST_DT_CORE_CLK = R9A09G047_USB2_0_CLK_CORE1,



	/* External Input Clocks */

	CLK_AUDIO_EXTAL,
@@ -177,6 +177,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 
		 CDDIV1_DIVCTL3, dtable_1_8),

	DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),

	DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),

	DEF_FIXED("usb2_0_clk_core0", R9A09G047_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),

	DEF_FIXED("usb2_0_clk_core1", R9A09G047_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),

	DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,

		  CLK_PLLETH_DIV_125_FIX, 1, 1),

	DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
@@ -282,6 +284,16 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 
						BUS_MSTOP(7, BIT(12))),

	DEF_MOD("usb3_0_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,

						BUS_MSTOP(7, BIT(14))),

	DEF_MOD("usb2_0_u2h0_hclk",		CLK_PLLDTY_DIV8, 11, 3, 5, 19,

						BUS_MSTOP(7, BIT(7))),

	DEF_MOD("usb2_0_u2h1_hclk",		CLK_PLLDTY_DIV8, 11, 4, 5, 20,

						BUS_MSTOP(7, BIT(8))),

	DEF_MOD("usb2_0_u2p_exr_cpuclk",	CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,

						BUS_MSTOP(7, BIT(9))),

	DEF_MOD("usb2_0_pclk_usbtst0",		CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,

						BUS_MSTOP(7, BIT(10))),

	DEF_MOD("usb2_0_pclk_usbtst1",		CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,

						BUS_MSTOP(7, BIT(11))),

	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,

						BUS_MSTOP(8, BIT(5)), 1),

	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -359,6 +371,10 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 
	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */

	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */

	DEF_RST(10, 10, 4, 27),		/* USB3_0_ARESETN */

	DEF_RST(10, 12, 4, 29),		/* USB2_0_U2H0_HRESETN */

	DEF_RST(10, 13, 4, 30),		/* USB2_0_U2H1_HRESETN */

	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */

	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */

	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */

	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */

	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */