Commit e44ee152 authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: Update P-state naming for clarity.



[Why & How]
P-state can refer to different things like UCLK P-state, PPT, or temp read
Update naming for clarity

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarRay Wu <ray.wu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9c83768e
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+1 −1
Original line number Diff line number Diff line
@@ -13024,7 +13024,7 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod
	out->informative.mode_support_info.InvalidCombinationOfMALLUseForPState = mode_lib->ms.support.InvalidCombinationOfMALLUseForPState;
	out->informative.mode_support_info.ExceededMALLSize = mode_lib->ms.support.ExceededMALLSize;
	out->informative.mode_support_info.EnoughWritebackUnits = mode_lib->ms.support.EnoughWritebackUnits;
	out->informative.mode_support_info.temp_read_or_ppt_support = mode_lib->ms.support.temp_read_or_ppt_support;
	out->informative.mode_support_info.temp_read_or_ppt_support = mode_lib->ms.support.global_temp_read_or_ppt_supported;
	out->informative.mode_support_info.g6_temp_read_support = mode_lib->ms.support.g6_temp_read_support;
	out->informative.mode_support_info.ExceededMultistreamSlots = mode_lib->ms.support.ExceededMultistreamSlots;
+12 −6
Original line number Diff line number Diff line
@@ -264,8 +264,11 @@ struct dml2_core_internal_mode_support_info {
	bool DCCMetaBufferSizeNotExceeded;
	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
	enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES];
	bool global_dram_clock_change_support_required;
	bool global_dram_clock_change_supported;
	bool global_fclk_change_supported;
	bool global_temp_read_or_ppt_supported;
	bool USRRetrainingSupport;
	bool AvgBandwidthSupport;
	bool UrgVactiveBandwidthSupport;
@@ -336,7 +339,6 @@ struct dml2_core_internal_mode_support_info {
	bool incorrect_imall_usage;

	bool g6_temp_read_support;
	bool temp_read_or_ppt_support;

	struct dml2_core_internal_watermarks watermarks;
	bool dcfclk_support;
@@ -646,7 +648,7 @@ struct dml2_core_internal_mode_support {
	unsigned int DSTYAfterScaler[DML2_MAX_PLANES];
	unsigned int DSTXAfterScaler[DML2_MAX_PLANES];

	enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES];
	enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES];
};

/// @brief A mega structure that houses various info for model programming step.
@@ -837,6 +839,7 @@ struct dml2_core_internal_mode_program {
	double max_urgent_latency_us;
	double df_response_time_us;

	enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES];
	// -------------------
	// Output
	// -------------------
@@ -963,11 +966,12 @@ struct dml2_core_internal_mode_program {
	double MaxActiveFCLKChangeLatencySupported;
	bool USRRetrainingSupport;
	bool g6_temp_read_support;
	bool temp_read_or_ppt_support;
	enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];
	enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];
	enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES];
	bool global_dram_clock_change_supported;
	bool global_fclk_change_supported;
	bool global_temp_read_or_ppt_supported;
	double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];
	double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES];
	double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES];
@@ -1313,7 +1317,7 @@ struct dml2_core_calcs_CalculateVMRowAndSwath_params {
	unsigned int HostVMMinPageSize;
	unsigned int DCCMetaBufferSizeBytes;
	bool mrq_present;
	enum dml2_pstate_method *pstate_switch_modes;
	enum dml2_pstate_method *uclk_pstate_switch_modes;

	// Output
	bool *PTEBufferSizeNotExceeded;
@@ -1740,10 +1744,12 @@ struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_param
	unsigned int max_request_size_bytes;
	unsigned int *meta_row_height_l;
	unsigned int *meta_row_height_c;
	enum dml2_pstate_method *uclk_pstate_switch_modes;

	// Output
	struct dml2_core_internal_watermarks *Watermark;
	enum dml2_pstate_change_support *DRAMClockChangeSupport;
	bool *global_dram_clock_change_support_required;
	bool *global_dram_clock_change_supported;
	double *MaxActiveDRAMClockChangeLatencySupported;
	unsigned int *SubViewportLinesNeededInMALL;
@@ -1754,10 +1760,10 @@ struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_param
	double *VActiveLatencyHidingMargin;
	double *VActiveLatencyHidingUs;
	bool *g6_temp_read_support;
	bool *temp_read_or_ppt_support;
	enum dml2_pstate_change_support *temp_read_or_ppt_support;
	bool *global_temp_read_or_ppt_supported;
};


struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params {
	const struct dml2_display_cfg *display_cfg;
	unsigned int ConfigReturnBufferSizeInKByte;
+2 −0
Original line number Diff line number Diff line
@@ -306,6 +306,8 @@ void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mod
		DML_LOG_VERBOSE("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize);
	if (!fail_only || support->g6_temp_read_support == 0)
		DML_LOG_VERBOSE("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support);
	if (!fail_only || (support->global_dram_clock_change_supported == 0 && support->global_dram_clock_change_support_required))
		DML_LOG_VERBOSE("DML: support: dram_clock_change_support = %d\n", support->global_dram_clock_change_supported);
	if (!fail_only || support->ImmediateFlipSupport == 0)
		DML_LOG_VERBOSE("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport);
	if (!fail_only || support->LinkCapacitySupport == 0)