Loading .clang-format +1 −0 Original line number Diff line number Diff line Loading @@ -748,6 +748,7 @@ ForEachMacros: - 'ynl_attr_for_each_nested' - 'ynl_attr_for_each_payload' - 'zorro_for_each_dev' - 'zpci_bus_for_each' IncludeBlocks: Preserve IncludeCategories: Loading CREDITS +1 −0 Original line number Diff line number Diff line Loading @@ -1987,6 +1987,7 @@ D: netfilter: TCP window tracking code D: netfilter: raw table D: netfilter: iprange match D: netfilter: new logging interfaces D: netfilter: ipset D: netfilter: various other hacks S: Tata S: Hungary Loading Documentation/admin-guide/blockdev/zoned_loop.rst +1 −1 Original line number Diff line number Diff line Loading @@ -134,7 +134,7 @@ MB and a zone capacity of 63 MB:: $ modprobe zloop $ mkdir -p /var/local/zloop/0 $ echo "add capacity_mb=2048,zone_size_mb=64,zone_capacity=63MB" > /dev/zloop-control $ echo "add capacity_mb=2048,zone_size_mb=64,zone_capacity_mb=63" > /dev/zloop-control For the device created (/dev/zloop0), the zone backing files are all created under the default base directory (/var/local/zloop):: Loading Documentation/arch/riscv/hwprobe.rst +8 −0 Original line number Diff line number Diff line Loading @@ -281,6 +281,14 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. Loading Documentation/arch/x86/boot.rst +99 −99 Original line number Diff line number Diff line Loading @@ -433,7 +433,7 @@ Protocol: 2.00+ Assigned boot loader IDs: == ======================================= ==== ======================================= 0x0 LILO (0x00 reserved for pre-2.00 bootloader) 0x1 Loadlin Loading @@ -456,7 +456,7 @@ Protocol: 2.00+ <http://sebastian-plotz.blogspot.de> 0x12 OVMF UEFI virtualization stack 0x13 barebox == ======================================= ==== ======================================= Please contact <hpa@zytor.com> if you need a bootloader ID value assigned. Loading Loading
.clang-format +1 −0 Original line number Diff line number Diff line Loading @@ -748,6 +748,7 @@ ForEachMacros: - 'ynl_attr_for_each_nested' - 'ynl_attr_for_each_payload' - 'zorro_for_each_dev' - 'zpci_bus_for_each' IncludeBlocks: Preserve IncludeCategories: Loading
CREDITS +1 −0 Original line number Diff line number Diff line Loading @@ -1987,6 +1987,7 @@ D: netfilter: TCP window tracking code D: netfilter: raw table D: netfilter: iprange match D: netfilter: new logging interfaces D: netfilter: ipset D: netfilter: various other hacks S: Tata S: Hungary Loading
Documentation/admin-guide/blockdev/zoned_loop.rst +1 −1 Original line number Diff line number Diff line Loading @@ -134,7 +134,7 @@ MB and a zone capacity of 63 MB:: $ modprobe zloop $ mkdir -p /var/local/zloop/0 $ echo "add capacity_mb=2048,zone_size_mb=64,zone_capacity=63MB" > /dev/zloop-control $ echo "add capacity_mb=2048,zone_size_mb=64,zone_capacity_mb=63" > /dev/zloop-control For the device created (/dev/zloop0), the zone backing files are all created under the default base directory (/var/local/zloop):: Loading
Documentation/arch/riscv/hwprobe.rst +8 −0 Original line number Diff line number Diff line Loading @@ -281,6 +281,14 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was mistakenly classified as a bitmask rather than a value. Loading
Documentation/arch/x86/boot.rst +99 −99 Original line number Diff line number Diff line Loading @@ -433,7 +433,7 @@ Protocol: 2.00+ Assigned boot loader IDs: == ======================================= ==== ======================================= 0x0 LILO (0x00 reserved for pre-2.00 bootloader) 0x1 Loadlin Loading @@ -456,7 +456,7 @@ Protocol: 2.00+ <http://sebastian-plotz.blogspot.de> 0x12 OVMF UEFI virtualization stack 0x13 barebox == ======================================= ==== ======================================= Please contact <hpa@zytor.com> if you need a bootloader ID value assigned. Loading