Commit e4710376 authored by Sameer Pujar's avatar Sameer Pujar Committed by Thierry Reding
Browse files

arm64: tegra: Audio graph sound card for Jetson TX2 



Enable support for audio-graph based sound card on Jetson TX2. Based
on the board design following I/O modules are enabled.
  * All I2S instances (I2S1 ... I2S6)
  * All DSPK instances (DSPK1, DSPK2)
  * DMIC1, DMIC2 and DMIC3

Signed-off-by: default avatarSameer Pujar <spujar@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 5d25c476

arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts

+730 −0
Original line number Diff line number Diff line
@@ -20,6 +20,713 @@ dma-controller@2930000 { 
		interrupt-controller@2a40000 {

			status = "okay";

		};



		ahub@2900800 {

			status = "okay";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0x0>;



					xbar_admaif0_ep: endpoint {

						remote-endpoint = <&admaif0_ep>;

					};

				};



				port@1 {

					reg = <0x1>;



					xbar_admaif1_ep: endpoint {

						remote-endpoint = <&admaif1_ep>;

					};

				};



				port@2 {

					reg = <0x2>;



					xbar_admaif2_ep: endpoint {

						remote-endpoint = <&admaif2_ep>;

					};

				};



				port@3 {

					reg = <0x3>;



					xbar_admaif3_ep: endpoint {

						remote-endpoint = <&admaif3_ep>;

					};

				};



				port@4 {

					reg = <0x4>;



					xbar_admaif4_ep: endpoint {

						remote-endpoint = <&admaif4_ep>;

					};

				};



				port@5 {

					reg = <0x5>;



					xbar_admaif5_ep: endpoint {

						remote-endpoint = <&admaif5_ep>;

					};

				};



				port@6 {

					reg = <0x6>;



					xbar_admaif6_ep: endpoint {

						remote-endpoint = <&admaif6_ep>;

					};

				};



				port@7 {

					reg = <0x7>;



					xbar_admaif7_ep: endpoint {

						remote-endpoint = <&admaif7_ep>;

					};

				};



				port@8 {

					reg = <0x8>;



					xbar_admaif8_ep: endpoint {

						remote-endpoint = <&admaif8_ep>;

					};

				};



				port@9 {

					reg = <0x9>;



					xbar_admaif9_ep: endpoint {

						remote-endpoint = <&admaif9_ep>;

					};

				};



				port@a {

					reg = <0xa>;



					xbar_admaif10_ep: endpoint {

						remote-endpoint = <&admaif10_ep>;

					};

				};



				port@b {

					reg = <0xb>;



					xbar_admaif11_ep: endpoint {

						remote-endpoint = <&admaif11_ep>;

					};

				};



				port@c {

					reg = <0xc>;



					xbar_admaif12_ep: endpoint {

						remote-endpoint = <&admaif12_ep>;

					};

				};



				port@d {

					reg = <0xd>;



					xbar_admaif13_ep: endpoint {

						remote-endpoint = <&admaif13_ep>;

					};

				};



				port@e {

					reg = <0xe>;



					xbar_admaif14_ep: endpoint {

						remote-endpoint = <&admaif14_ep>;

					};

				};



				port@f {

					reg = <0xf>;



					xbar_admaif15_ep: endpoint {

						remote-endpoint = <&admaif15_ep>;

					};

				};



				port@10 {

					reg = <0x10>;



					xbar_admaif16_ep: endpoint {

						remote-endpoint = <&admaif16_ep>;

					};

				};



				port@11 {

					reg = <0x11>;



					xbar_admaif17_ep: endpoint {

						remote-endpoint = <&admaif17_ep>;

					};

				};



				port@12 {

					reg = <0x12>;



					xbar_admaif18_ep: endpoint {

						remote-endpoint = <&admaif18_ep>;

					};

				};



				port@13 {

					reg = <0x13>;



					xbar_admaif19_ep: endpoint {

						remote-endpoint = <&admaif19_ep>;

					};

				};



				xbar_i2s1_port: port@14 {

					reg = <0x14>;



					xbar_i2s1_ep: endpoint {

						remote-endpoint = <&i2s1_cif_ep>;

					};

				};



				xbar_i2s2_port: port@15 {

					reg = <0x15>;



					xbar_i2s2_ep: endpoint {

						remote-endpoint = <&i2s2_cif_ep>;

					};

				};



				xbar_i2s3_port: port@16 {

					reg = <0x16>;



					xbar_i2s3_ep: endpoint {

						remote-endpoint = <&i2s3_cif_ep>;

					};

				};



				xbar_i2s4_port: port@17 {

					reg = <0x17>;



					xbar_i2s4_ep: endpoint {

						remote-endpoint = <&i2s4_cif_ep>;

					};

				};



				xbar_i2s5_port: port@18 {

					reg = <0x18>;



					xbar_i2s5_ep: endpoint {

						remote-endpoint = <&i2s5_cif_ep>;

					};

				};



				xbar_i2s6_port: port@19 {

					reg = <0x19>;



					xbar_i2s6_ep: endpoint {

						remote-endpoint = <&i2s6_cif_ep>;

					};

				};



				xbar_dmic1_port: port@1a {

					reg = <0x1a>;



					xbar_dmic1_ep: endpoint {

						remote-endpoint = <&dmic1_cif_ep>;

					};

				};



				xbar_dmic2_port: port@1b {

					reg = <0x1b>;



					xbar_dmic2_ep: endpoint {

						remote-endpoint = <&dmic2_cif_ep>;

					};

				};



				xbar_dmic3_port: port@1c {

					reg = <0x1c>;



					xbar_dmic3_ep: endpoint {

						remote-endpoint = <&dmic3_cif_ep>;

					};

				};



				xbar_dspk1_port: port@1e {

					reg = <0x1e>;



					xbar_dspk1_ep: endpoint {

						remote-endpoint = <&dspk1_cif_ep>;

					};

				};



				xbar_dspk2_port: port@1f {

					reg = <0x1f>;



					xbar_dspk2_ep: endpoint {

						remote-endpoint = <&dspk2_cif_ep>;

					};

				};

			};



			admaif@290f000 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					admaif0_port: port@0 {

						reg = <0x0>;



						admaif0_ep: endpoint {

							remote-endpoint = <&xbar_admaif0_ep>;

						};

					};



					admaif1_port: port@1 {

						reg = <0x1>;



						admaif1_ep: endpoint {

							remote-endpoint = <&xbar_admaif1_ep>;

						};

					};



					admaif2_port: port@2 {

						reg = <0x2>;



						admaif2_ep: endpoint {

							remote-endpoint = <&xbar_admaif2_ep>;

						};

					};



					admaif3_port: port@3 {

						reg = <0x3>;



						admaif3_ep: endpoint {

							remote-endpoint = <&xbar_admaif3_ep>;

						};

					};



					admaif4_port: port@4 {

						reg = <0x4>;



						admaif4_ep: endpoint {

							remote-endpoint = <&xbar_admaif4_ep>;

						};

					};



					admaif5_port: port@5 {

						reg = <0x5>;



						admaif5_ep: endpoint {

							remote-endpoint = <&xbar_admaif5_ep>;

						};

					};



					admaif6_port: port@6 {

						reg = <0x6>;



						admaif6_ep: endpoint {

							remote-endpoint = <&xbar_admaif6_ep>;

						};

					};



					admaif7_port: port@7 {

						reg = <0x7>;



						admaif7_ep: endpoint {

							remote-endpoint = <&xbar_admaif7_ep>;

						};

					};



					admaif8_port: port@8 {

						reg = <0x8>;



						admaif8_ep: endpoint {

							remote-endpoint = <&xbar_admaif8_ep>;

						};

					};



					admaif9_port: port@9 {

						reg = <0x9>;



						admaif9_ep: endpoint {

							remote-endpoint = <&xbar_admaif9_ep>;

						};

					};



					admaif10_port: port@a {

						reg = <0xa>;



						admaif10_ep: endpoint {

							remote-endpoint = <&xbar_admaif10_ep>;

						};

					};



					admaif11_port: port@b {

						reg = <0xb>;



						admaif11_ep: endpoint {

							remote-endpoint = <&xbar_admaif11_ep>;

						};

					};



					admaif12_port: port@c {

						reg = <0xc>;



						admaif12_ep: endpoint {

							remote-endpoint = <&xbar_admaif12_ep>;

						};

					};



					admaif13_port: port@d {

						reg = <0xd>;



						admaif13_ep: endpoint {

							remote-endpoint = <&xbar_admaif13_ep>;

						};

					};



					admaif14_port: port@e {

						reg = <0xe>;



						admaif14_ep: endpoint {

							remote-endpoint = <&xbar_admaif14_ep>;

						};

					};



					admaif15_port: port@f {

						reg = <0xf>;



						admaif15_ep: endpoint {

							remote-endpoint = <&xbar_admaif15_ep>;

						};

					};



					admaif16_port: port@10 {

						reg = <0x10>;



						admaif16_ep: endpoint {

							remote-endpoint = <&xbar_admaif16_ep>;

						};

					};



					admaif17_port: port@11 {

						reg = <0x11>;



						admaif17_ep: endpoint {

							remote-endpoint = <&xbar_admaif17_ep>;

						};

					};



					admaif18_port: port@12 {

						reg = <0x12>;



						admaif18_ep: endpoint {

							remote-endpoint = <&xbar_admaif18_ep>;

						};

					};



					admaif19_port: port@13 {

						reg = <0x13>;



						admaif19_ep: endpoint {

							remote-endpoint = <&xbar_admaif19_ep>;

						};

					};

				};

			};



			i2s@2901000 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						i2s1_cif_ep: endpoint {

							remote-endpoint = <&xbar_i2s1_ep>;

						};

					};



					i2s1_port: port@1 {

						reg = <1>;



						i2s1_dap_ep: endpoint {

							dai-format = "i2s";

							/* Placeholder for external Codec */

						};

					};

				};

			};



			i2s@2901100 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						i2s2_cif_ep: endpoint {

							remote-endpoint = <&xbar_i2s2_ep>;

						};

					};



					i2s2_port: port@1 {

						reg = <1>;



						i2s2_dap_ep: endpoint {

							dai-format = "i2s";

							/* Placeholder for external Codec */

						};

					};

				};

			};



			i2s@2901200 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						i2s3_cif_ep: endpoint {

							remote-endpoint = <&xbar_i2s3_ep>;

						};

					};



					i2s3_port: port@1 {

						reg = <1>;



						i2s3_dap_ep: endpoint {

							dai-format = "i2s";

							/* Placeholder for external Codec */

						};

					};

				};

			};



			i2s@2901300 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						i2s4_cif_ep: endpoint {

							remote-endpoint = <&xbar_i2s4_ep>;

						};

					};



					i2s4_port: port@1 {

						reg = <1>;



						i2s4_dap_ep: endpoint {

							dai-format = "i2s";

							/* Placeholder for external Codec */

						};

					};

				};

			};



			i2s@2901400 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						i2s5_cif_ep: endpoint {

							remote-endpoint = <&xbar_i2s5_ep>;

						};

					};



					i2s5_port: port@1 {

						reg = <1>;



						i2s5_dap_ep: endpoint {

							dai-format = "i2s";

							/* Placeholder for external Codec */

						};

					};

				};

			};



			i2s@2901500 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						i2s6_cif_ep: endpoint {

							remote-endpoint = <&xbar_i2s6_ep>;

						};

					};



					i2s6_port: port@1 {

						reg = <1>;



						i2s6_dap_ep: endpoint {

							dai-format = "i2s";

							/* Placeholder for external Codec */

						};

					};

				};

			};



			dmic@2904000 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dmic1_cif_ep: endpoint {

							remote-endpoint = <&xbar_dmic1_ep>;

						};

					};



					dmic1_port: port@1 {

						reg = <1>;



						dmic1_dap_ep: endpoint {

							/* Place holder for external Codec */

						};

					};

				};

			};



			dmic@2904100 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dmic2_cif_ep: endpoint {

							remote-endpoint = <&xbar_dmic2_ep>;

						};

					};



					dmic2_port: port@1 {

						reg = <1>;



						dmic2_dap_ep: endpoint {

							/* Place holder for external Codec */

						};

					};

				};

			};



			dmic@2904200 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dmic3_cif_ep: endpoint {

							remote-endpoint = <&xbar_dmic3_ep>;

						};

					};



					dmic3_port: port@1 {

						reg = <1>;



						dmic3_dap_ep: endpoint {

							/* Place holder for external Codec */

						};

					};

				};

			};



			dspk@2905000 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dspk1_cif_ep: endpoint {

							remote-endpoint = <&xbar_dspk1_ep>;

						};

					};



					dspk1_port: port@1 {

						reg = <1>;



						dspk1_dap_ep: endpoint {

							/* Place holder for external Codec */

						};

					};

				};

			};



			dspk@2905100 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;



						dspk2_cif_ep: endpoint {

							remote-endpoint = <&xbar_dspk2_ep>;

						};

					};



					dspk2_port: port@1 {

						reg = <1>;



						dspk2_dap_ep: endpoint {

							/* Place holder for external Codec */

						};

					};

				};

			};

		};

	};



	i2c@3160000 {
@@ -381,4 +1088,27 @@ vdd_usb1: regulator@103 { 


		vin-supply = <&vdd_5v0_sys>;

	};



	sound {

		compatible = "nvidia,tegra186-audio-graph-card";

		status = "okay";



		dais = /* FE */

		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,

		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,

		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,

		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,

		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,

		       /* Router */

		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,

		       <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_i2s6_port>,

		       <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic3_port>,

		       <&xbar_dspk1_port>, <&xbar_dspk2_port>,

		       /* I/O */

		       <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,

		       <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,

		       <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;



		label = "jetson-tx2-ape";

	};

};

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -1678,6 +1678,28 @@ pmu_a57 { 
		interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;

	};



	sound {

		status = "disabled";



		clocks = <&bpmp TEGRA186_CLK_PLLA>,

			 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;

		clock-names = "pll_a", "plla_out0";

		assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,

				  <&bpmp TEGRA186_CLK_PLL_A_OUT0>,

				  <&bpmp TEGRA186_CLK_AUD_MCLK>;

		assigned-clock-parents = <0>,

					 <&bpmp TEGRA186_CLK_PLLA>,

					 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;

		/*

		 * PLLA supports dynamic ramp. Below initial rate is chosen

		 * for this to work and oscillate between base rates required

		 * for 8x and 11.025x sample rate streams.

		 */

		assigned-clock-rates = <258000000>;



		iommus = <&smmu TEGRA186_SID_APE>;

	};



	thermal-zones {

		a57 {

			polling-delay = <0>;