Commit e4b700d3 authored by Inochi Amaoto's avatar Inochi Amaoto
Browse files

dt-bindings: soc: sophgo: Add SG2044 top syscon device 



The SG2044 top syscon device provide PLL clock control and some other
misc feature of the SoC.

Add the compatible string for SG2044 top syscon device.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250418020325.421257-2-inochiama@gmail.com


Signed-off-by: default avatarInochi Amaoto <inochiama@gmail.com>
Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>
Signed-off-by: default avatarChen Wang <wangchen20@iscas.ac.cn>
parent dd8bbae9

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2044 SoC TOP system controller



maintainers:

  - Inochi Amaoto <inochiama@gmail.com>



description:

  The Sophgo SG2044 TOP system controller is a hardware block grouping

  multiple small functions, such as clocks and some other internal

  function.



properties:

  compatible:

    items:

      - const: sophgo,sg2044-top-syscon

      - const: syscon



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2044-pll.h> for valid clock.



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    syscon@50000000 {

      compatible = "sophgo,sg2044-top-syscon", "syscon";

      reg = <0x50000000 0x1000>;

      #clock-cells = <1>;

      clocks = <&osc>;

    };

include/dt-bindings/clock/sophgo,sg2044-pll.h

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/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */

/*

 * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com>

 */



#ifndef __DT_BINDINGS_SOPHGO_SG2044_PLL_H__

#define __DT_BINDINGS_SOPHGO_SG2044_PLL_H__



#define CLK_FPLL0			0

#define CLK_FPLL1			1

#define CLK_FPLL2			2

#define CLK_DPLL0			3

#define CLK_DPLL1			4

#define CLK_DPLL2			5

#define CLK_DPLL3			6

#define CLK_DPLL4			7

#define CLK_DPLL5			8

#define CLK_DPLL6			9

#define CLK_DPLL7			10

#define CLK_MPLL0			11

#define CLK_MPLL1			12

#define CLK_MPLL2			13

#define CLK_MPLL3			14

#define CLK_MPLL4			15

#define CLK_MPLL5			16



#endif /* __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ */