Unverified Commit e4c7dfd9 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Krzysztof Wilczyński
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PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() 

In order to make the code more readable, the reset_control_bulk_assert()
function for PHY reset lines is moved to make it pair with
reset_control_bulk_deassert() in mtk_pcie_power_up() and
mtk_pcie_en7581_power_up(). The same change is done for
reset_control_assert() used to assert MAC reset line.

Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to
complete PCIe reset on MediaTek controller.

Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-2-21ac939a3b9b@kernel.org


Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
parent 0e7a622d

drivers/pci/controller/pcie-mediatek-gen3.c

+18 −10
Original line number Diff line number Diff line
@@ -125,6 +125,8 @@ 


#define MAX_NUM_PHY_RESETS		3



#define PCIE_MTK_RESET_TIME_US		10



/* Time in ms needed to complete PCIe reset on EN7581 SoC */

#define PCIE_EN7581_RESET_TIME_MS	100
@@ -913,9 +915,14 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) 
	u32 val;



	/*

	 * Wait for the time needed to complete the bulk assert in

	 * mtk_pcie_setup for EN7581 SoC.

	 * The controller may have been left out of reset by the bootloader

	 * so make sure that we get a clean start by asserting resets here.

	 */

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

				  pcie->phy_resets);

	reset_control_assert(pcie->mac_reset);



	/* Wait for the time needed to complete the reset lines assert. */

	mdelay(PCIE_EN7581_RESET_TIME_MS);



	err = phy_init(pcie->phy);
@@ -982,6 +989,15 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) 
	struct device *dev = pcie->dev;

	int err;



	/*

	 * The controller may have been left out of reset by the bootloader

	 * so make sure that we get a clean start by asserting resets here.

	 */

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,

				  pcie->phy_resets);

	reset_control_assert(pcie->mac_reset);

	usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US);



	/* PHY power on and enable pipe clock */

	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	if (err) {
@@ -1066,14 +1082,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) 
	 * counter since the bulk is shared.

	 */

	reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);

	/*

	 * The controller may have been left out of reset by the bootloader

	 * so make sure that we get a clean start by asserting resets here.

	 */

	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);



	reset_control_assert(pcie->mac_reset);

	usleep_range(10, 20);



	/* Don't touch the hardware registers before power up */

	err = pcie->soc->power_up(pcie);