Commit e4d0c909 authored by Kamil Horák - 2N's avatar Kamil Horák - 2N Committed by Jakub Kicinski
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net: phy: bcm54811: Fix GMII/MII/MII-Lite selection 



The Broadcom bcm54811 is hardware-strapped to select among RGMII and
GMII/MII/MII-Lite modes. However, the corresponding bit, RGMII Enable
in Miscellaneous Control Register must be also set to select desired
RGMII or MII(-lite)/GMII mode.

Fixes: 3117a11f ("net: phy: bcm54811: PHY initialization")
Signed-off-by: default avatarKamil Horák - 2N <kamilh@axis.com>
Reviewed-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20251009130656.1308237-2-kamilh@axis.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 70f92ab9

drivers/net/phy/broadcom.c

+19 −1
Original line number Diff line number Diff line
@@ -405,7 +405,7 @@ static int bcm5481x_set_brrmode(struct phy_device *phydev, bool on) 
static int bcm54811_config_init(struct phy_device *phydev)

{

	struct bcm54xx_phy_priv *priv = phydev->priv;

	int err, reg, exp_sync_ethernet;

	int err, reg, exp_sync_ethernet, aux_rgmii_en;



	/* Enable CLK125 MUX on LED4 if ref clock is enabled. */

	if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
@@ -434,6 +434,24 @@ static int bcm54811_config_init(struct phy_device *phydev) 
	if (err < 0)

		return err;



	/* Enable RGMII if configured */

	if (phy_interface_is_rgmii(phydev))

		aux_rgmii_en = MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN |

			       MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;

	else

		aux_rgmii_en = 0;



	/* Also writing Reserved bits 6:5 because the documentation requires

	 * them to be written to 0b11

	 */

	err = bcm54xx_auxctl_write(phydev,

				   MII_BCM54XX_AUXCTL_SHDWSEL_MISC,

				   MII_BCM54XX_AUXCTL_MISC_WREN |

				   aux_rgmii_en |

				   MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RSVD);

	if (err < 0)

		return err;



	return bcm5481x_set_brrmode(phydev, priv->brr_mode);

}

include/linux/brcmphy.h

+1 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ 


#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC			0x07

#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN	0x0010

#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RSVD		0x0060

#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN	0x0080

#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN	0x0100

#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX		0x0200