Commit e54478fb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.8-2024-01-05' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-6.8-2024-01-05:

amdgpu:
- VRR fixes
- PSR-SU fixes
- SubVP fixes
- DCN 3.5 fixes
- Documentation updates
- DMCUB fixes
- DML2 fixes
- UMC 12.0 updates
- GPUVM fix
- Misc code cleanups and whitespace cleanups
- DP MST fix
- Let KFD sync with GPUVM fences
- GFX11 reset fix
- SMU 13.0.6 fixes
- VSC fix for DP/eDP
- Navi12 display fix
- RN/CZN system aperture fix
- DCN 2.1 bandwidth validation fix
- DCN INIT cleanup

amdkfd:
- SVM fixes
- Revert TBA/TMA location change

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240105220522.4976-1-alexander.deucher@amd.com
parents 3c064aea 754d349e

Documentation/gpu/amdgpu/apu-asic-info-table.csv

+3 −2
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1, 11.5.0 
Ryzen 5000 series / Ryzen 7x30 series, GREEN SARDINE / Cezanne / Barcelo / Barcelo-R, DCN 2.1, 9.3, VCN 2.2, 4.1.1, 12.0.1

Ryzen 6000 series / Ryzen 7x35 series / Ryzen 7x36 series, YELLOW CARP / Rembrandt / Rembrandt-R, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3

Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5

Ryzen 7x45 series (FL1), / Dragon Range, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5

Ryzen 7x45 series (FL1), Dragon Range, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5

Ryzen 7x20 series, Mendocino, 3.1.6, 10.3.7, 3.1.1, 5.2.7, 13.0.8

Ryzen 7x40 series, Phoenix, 3.1.4, 11.0.1 / 11.0.4, 4.0.2, 6.0.1, 13.0.4 / 13.0.11

Ryzen 8x40 series, Hawk Point, 3.1.4, 11.0.1 / 11.0.4, 4.0.2, 6.0.1, 13.0.4 / 13.0.11

drivers/gpu/drm/amd/amdgpu/aldebaran.c

+25 −1
Original line number Diff line number Diff line
@@ -330,6 +330,7 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 
{

	struct list_head *reset_device_list = reset_context->reset_device_list;

	struct amdgpu_device *tmp_adev = NULL;

	struct amdgpu_ras *con;

	int r;



	if (reset_device_list == NULL)
@@ -355,7 +356,30 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 
		 */

		amdgpu_register_gpu_instance(tmp_adev);



		/* Resume RAS */

		/* Resume RAS, ecc_irq */

		con = amdgpu_ras_get_context(tmp_adev);

		if (!amdgpu_sriov_vf(tmp_adev) && con) {

			if (tmp_adev->sdma.ras &&

				tmp_adev->sdma.ras->ras_block.ras_late_init) {

				r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,

						&tmp_adev->sdma.ras->ras_block.ras_comm);

				if (r) {

					dev_err(tmp_adev->dev, "SDMA failed to execute ras_late_init! ret:%d\n", r);

					goto end;

				}

			}



			if (tmp_adev->gfx.ras &&

				tmp_adev->gfx.ras->ras_block.ras_late_init) {

				r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,

						&tmp_adev->gfx.ras->ras_block.ras_comm);

				if (r) {

					dev_err(tmp_adev->dev, "GFX failed to execute ras_late_init! ret:%d\n", r);

					goto end;

				}

			}

		}



		amdgpu_ras_resume(tmp_adev);



		/* Update PSP FW topology after reset */

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −0
Original line number Diff line number Diff line
@@ -254,6 +254,8 @@ extern int amdgpu_agp; 


extern int amdgpu_wbrf;



extern int fw_bo_location;



#define AMDGPU_VM_MAX_NUM_CTX			4096

#define AMDGPU_SG_THRESHOLD			(256*1024*1024)

#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

+1 −1
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 
		return NULL;



	fence = container_of(f, struct amdgpu_amdkfd_fence, base);

	if (fence && f->ops == &amdkfd_fence_ops)

	if (f->ops == &amdkfd_fence_ops)

		return fence;



	return NULL;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+3 −3
Original line number Diff line number Diff line
@@ -870,9 +870,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
		struct amdgpu_bo *bo = e->bo;

		int i;



		e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,

		e->user_pages = kvcalloc(bo->tbo.ttm->num_pages,

					 sizeof(struct page *),

					GFP_KERNEL | __GFP_ZERO);

					 GFP_KERNEL);

		if (!e->user_pages) {

			DRM_ERROR("kvmalloc_array failure\n");

			r = -ENOMEM;