Unverified Commit e576b7cb authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
Browse files

dt-bindings: riscv: Add xtheadvector ISA extension description 

The xtheadvector ISA extension is described on the T-Head extension spec
Github page [1] at commit 95358cb2cca9.

Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc

 [1]

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Tested-by: default avatarYangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-1-236c22791ef9@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 9d87cf52

Documentation/devicetree/bindings/riscv/extensions.yaml

+10 −0
Original line number Diff line number Diff line
@@ -593,6 +593,10 @@ properties: 
            latency, as ratified in commit 56ed795 ("Update

            riscv-crypto-spec-vector.adoc") of riscv-crypto.



        # vendor extensions, each extension sorted alphanumerically under the

        # vendor they belong to. Vendors are sorted alphanumerically as well.



        # Andes

        - const: xandespmu

          description:

            The Andes Technology performance monitor extension for counter overflow
@@ -600,6 +604,12 @@ properties: 
            Registers in the AX45MP datasheet.

            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf



        # T-HEAD

        - const: xtheadvector

          description:

            The T-HEAD specific 0.7.1 vector implementation as written in

            https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.



    allOf:

      # Zcb depends on Zca

      - if: