Commit e5ad7177 authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amdgpu: Add compatible NPS mode info



Populate the compatible NPS modes also for providing partition
configuration details through sysfs.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 81db4eab
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+1 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ struct amdgpu_xcp_cfg {
	u8 num_res;
	struct amdgpu_xcp_mgr *xcp_mgr;
	struct kobject kobj;
	u16 compatible_nps_modes;
};

struct amdgpu_xcp_ip_funcs {
+11 −0
Original line number Diff line number Diff line
@@ -455,6 +455,7 @@ static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr,
	int max_res[AMDGPU_XCP_RES_MAX] = {};
	bool res_lt_xcp;
	int num_xcp, i;
	u16 nps_modes;

	if (!(xcp_mgr->supp_xcp_modes & BIT(mode)))
		return -EINVAL;
@@ -467,23 +468,33 @@ static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr,
	switch (mode) {
	case AMDGPU_SPX_PARTITION_MODE:
		num_xcp = 1;
		nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
		break;
	case AMDGPU_DPX_PARTITION_MODE:
		num_xcp = 2;
		nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE);
		break;
	case AMDGPU_TPX_PARTITION_MODE:
		num_xcp = 3;
		nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
			    BIT(AMDGPU_NPS4_PARTITION_MODE);
		break;
	case AMDGPU_QPX_PARTITION_MODE:
		num_xcp = 4;
		nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
			    BIT(AMDGPU_NPS4_PARTITION_MODE);
		break;
	case AMDGPU_CPX_PARTITION_MODE:
		num_xcp = NUM_XCC(adev->gfx.xcc_mask);
		nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) |
			    BIT(AMDGPU_NPS4_PARTITION_MODE);
		break;
	default:
		return -EINVAL;
	}

	xcp_cfg->compatible_nps_modes =
		(adev->gmc.supported_nps_modes & nps_modes);
	xcp_cfg->num_res = ARRAY_SIZE(max_res);

	for (i = 0; i < xcp_cfg->num_res; i++) {