Commit e5bc76b0 authored by Jan Kuliga's avatar Jan Kuliga Committed by Vinod Koul
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dmaengine: xilinx: xdma: Ease dma_pool alignment requirements 



According to the XDMA datasheet (PG195), the address of any descriptor
must be 32 byte aligned. The datasheet also states that a contiguous
block of descriptors must not cross a 4k address boundary. Therefore,
it is possible to ease the pressure put on the dma_pool allocator
just by requiring sufficient alignment and boundary values. Add proper
macro definition and change the values passed into the
dma_pool_create().

Signed-off-by: default avatarJan Kuliga <jankul@alatek.krakow.pl>
Link: https://lore.kernel.org/r/20231218113943.9099-4-jankul@alatek.krakow.pl


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 7a9c7f46

drivers/dma/xilinx/xdma-regs.h

+4 −3
Original line number Diff line number Diff line
@@ -66,7 +66,8 @@ struct xdma_hw_desc { 


#define XDMA_DESC_SIZE			sizeof(struct xdma_hw_desc)

#define XDMA_DESC_BLOCK_SIZE		(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)

#define XDMA_DESC_BLOCK_ALIGN	4096

#define XDMA_DESC_BLOCK_ALIGN		32

#define XDMA_DESC_BLOCK_BOUNDARY	4096



/*

 * Channel registers

drivers/dma/xilinx/xdma.c

+2 −3
Original line number Diff line number Diff line
@@ -741,9 +741,8 @@ static int xdma_alloc_chan_resources(struct dma_chan *chan) 
		return -EINVAL;

	}



	xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan),

					       dev, XDMA_DESC_BLOCK_SIZE,

					       XDMA_DESC_BLOCK_ALIGN, 0);

	xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan), dev, XDMA_DESC_BLOCK_SIZE,

					       XDMA_DESC_BLOCK_ALIGN, XDMA_DESC_BLOCK_BOUNDARY);

	if (!xdma_chan->desc_pool) {

		xdma_err(xdev, "unable to allocate descriptor pool");

		return -ENOMEM;