Commit e5d3a578 authored by Dave Hansen's avatar Dave Hansen
Browse files

x86/cpu: Make all all CPUID leaf names consistent 



The leaf names are not consistent.  Give them all a CPUID_LEAF_ prefix
for consistency and vertical alignment.

Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Acked-by: Dave Jiang <dave.jiang@intel.com> # for ioatdma bits
Link: https://lore.kernel.org/all/20241213205040.7B0C3241%40davehans-spike.ostc.intel.com
parent 588e148d

arch/x86/events/intel/pt.c

+2 −2
Original line number Diff line number Diff line
@@ -202,10 +202,10 @@ static int __init pt_pmu_hw_init(void) 
	 * otherwise, zero for numerator stands for "not enumerated"

	 * as per SDM

	 */

	if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {

	if (boot_cpu_data.cpuid_level >= CPUID_LEAF_TSC) {

		u32 eax, ebx, ecx, edx;



		cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);

		cpuid(CPUID_LEAF_TSC, &eax, &ebx, &ecx, &edx);



		pt_pmu.tsc_art_num = ebx;

		pt_pmu.tsc_art_den = eax;

arch/x86/include/asm/cpuid.h

+6 −6
Original line number Diff line number Diff line
@@ -21,12 +21,12 @@ enum cpuid_regs_idx { 
	CPUID_EDX,

};



#define CPUID_MWAIT_LEAF	0x5

#define CPUID_DCA_LEAF		0x9

#define XSTATE_CPUID		0x0d

#define CPUID_TSC_LEAF		0x15

#define CPUID_FREQ_LEAF		0x16

#define TILE_CPUID		0x1d

#define CPUID_LEAF_MWAIT	0x5

#define CPUID_LEAF_DCA		0x9

#define CPUID_LEAF_XSTATE	0x0d

#define CPUID_LEAF_TSC		0x15

#define CPUID_LEAF_FREQ		0x16

#define CPUID_LEAF_TILE		0x1d



#ifdef CONFIG_X86_32

bool have_cpuid_p(void);

arch/x86/kernel/acpi/cstate.c

+2 −2
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static long acpi_processor_ffh_cstate_probe_cpu(void *_cx) 
	unsigned int cstate_type; /* C-state type and not ACPI C-state type */

	unsigned int num_cstate_subtype;



	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);

	cpuid(CPUID_LEAF_MWAIT, &eax, &ebx, &ecx, &edx);



	/* Check whether this particular cx_type (in CST) is supported or not */

	cstate_type = (((cx->address >> MWAIT_SUBSTATE_SIZE) &
@@ -173,7 +173,7 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu, 
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	long retval;



	if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)

	if (!cpu_cstate_entry || c->cpuid_level < CPUID_LEAF_MWAIT)

		return -1;



	if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)

arch/x86/kernel/cpu/common.c

+3 −3
Original line number Diff line number Diff line
@@ -637,9 +637,9 @@ struct cpuid_dependent_feature { 


static const struct cpuid_dependent_feature

cpuid_dependent_features[] = {

	{ X86_FEATURE_MWAIT,		CPUID_MWAIT_LEAF },

	{ X86_FEATURE_DCA,		CPUID_DCA_LEAF },

	{ X86_FEATURE_XSAVE,		XSTATE_CPUID },

	{ X86_FEATURE_MWAIT,		CPUID_LEAF_MWAIT },

	{ X86_FEATURE_DCA,		CPUID_LEAF_DCA },

	{ X86_FEATURE_XSAVE,		CPUID_LEAF_XSTATE },

	{ 0, 0 }

};

arch/x86/kernel/fpu/xstate.c

+10 −10
Original line number Diff line number Diff line
@@ -233,7 +233,7 @@ static void __init setup_xstate_cache(void) 
						       xmm_space);



	for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {

		cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);

		cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx);



		xstate_sizes[i] = eax;

		xstate_flags[i] = ecx;
@@ -399,7 +399,7 @@ int xfeature_size(int xfeature_nr) 
	u32 eax, ebx, ecx, edx;



	CHECK_XFEATURE(xfeature_nr);

	cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);

	cpuid_count(CPUID_LEAF_XSTATE, xfeature_nr, &eax, &ebx, &ecx, &edx);

	return eax;

}
@@ -442,9 +442,9 @@ static void __init __xstate_dump_leaves(void) 
	 * just in case there are some goodies up there

	 */

	for (i = 0; i < XFEATURE_MAX + 10; i++) {

		cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);

		cpuid_count(CPUID_LEAF_XSTATE, i, &eax, &ebx, &ecx, &edx);

		pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n",

			XSTATE_CPUID, i, eax, ebx, ecx, edx);

			CPUID_LEAF_XSTATE, i, eax, ebx, ecx, edx);

	}

}
@@ -485,7 +485,7 @@ static int __init check_xtile_data_against_struct(int size) 
	 * Check the maximum palette id:

	 *   eax: the highest numbered palette subleaf.

	 */

	cpuid_count(TILE_CPUID, 0, &max_palid, &ebx, &ecx, &edx);

	cpuid_count(CPUID_LEAF_TILE, 0, &max_palid, &ebx, &ecx, &edx);



	/*

	 * Cross-check each tile size and find the maximum number of
@@ -499,7 +499,7 @@ static int __init check_xtile_data_against_struct(int size) 
		 *   eax[31:16]:  bytes per title

		 *   ebx[31:16]:  the max names (or max number of tiles)

		 */

		cpuid_count(TILE_CPUID, palid, &eax, &ebx, &edx, &edx);

		cpuid_count(CPUID_LEAF_TILE, palid, &eax, &ebx, &edx, &edx);

		tile_size = eax >> 16;

		max = ebx >> 16;
@@ -634,7 +634,7 @@ static unsigned int __init get_compacted_size(void) 
	 * are no supervisor states, but XSAVEC still uses compacted

	 * format.

	 */

	cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);

	cpuid_count(CPUID_LEAF_XSTATE, 1, &eax, &ebx, &ecx, &edx);

	return ebx;

}
@@ -675,7 +675,7 @@ static unsigned int __init get_xsave_size_user(void) 
	 *    containing all the *user* state components

	 *    corresponding to bits currently set in XCR0.

	 */

	cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);

	cpuid_count(CPUID_LEAF_XSTATE, 0, &eax, &ebx, &ecx, &edx);

	return ebx;

}
@@ -767,13 +767,13 @@ void __init fpu__init_system_xstate(unsigned int legacy_size) 
	/*

	 * Find user xstates supported by the processor.

	 */

	cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);

	cpuid_count(CPUID_LEAF_XSTATE, 0, &eax, &ebx, &ecx, &edx);

	fpu_kernel_cfg.max_features = eax + ((u64)edx << 32);



	/*

	 * Find supervisor xstates supported by the processor.

	 */

	cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);

	cpuid_count(CPUID_LEAF_XSTATE, 1, &eax, &ebx, &ecx, &edx);

	fpu_kernel_cfg.max_features |= ecx + ((u64)edx << 32);



	if ((fpu_kernel_cfg.max_features & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) {