Commit e5ecedcd authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64/sysreg: Get rid of CPACR_ELx SysregFields 



There is no such thing as CPACR_ELx in the architecture.
What we have is CPACR_EL1, for which CPTR_EL12 is an accessor.

Rename CPACR_ELx_* to CPACR_EL1_*, and fix the bit of code using
these names.

Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241219173351.1123087-5-maz@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 233fc36b

arch/arm64/include/asm/el2_setup.h

+3 −3
Original line number Diff line number Diff line
@@ -154,7 +154,7 @@ 
/* Coprocessor traps */

.macro __init_el2_cptr

	__check_hvhe .LnVHE_\@, x1

	mov	x0, #CPACR_ELx_FPEN

	mov	x0, #CPACR_EL1_FPEN

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_\@

.LnVHE_\@:
@@ -332,7 +332,7 @@ 


	// (h)VHE case

	mrs	x0, cpacr_el1			// Disable SVE traps

	orr	x0, x0, #CPACR_ELx_ZEN

	orr	x0, x0, #CPACR_EL1_ZEN

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_\@
@@ -353,7 +353,7 @@ 


	// (h)VHE case

	mrs	x0, cpacr_el1			// Disable SME traps

	orr	x0, x0, #CPACR_ELx_SMEN

	orr	x0, x0, #CPACR_EL1_SMEN

	msr	cpacr_el1, x0

	b	.Lskip_set_cptr_sme_\@

arch/arm64/include/asm/kvm_arm.h

+0 −2
Original line number Diff line number Diff line
@@ -391,8 +391,6 @@ 
	ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \

	ECN(BKPT32), ECN(VECTOR32), ECN(BRK64), ECN(ERET)



#define CPACR_EL1_TTA		(1 << 28)



#define kvm_mode_names				\

	{ PSR_MODE_EL0t,	"EL0t" },	\

	{ PSR_MODE_EL1t,	"EL1t" },	\

arch/arm64/include/asm/kvm_emulate.h

+20 −20
Original line number Diff line number Diff line
@@ -556,13 +556,13 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 
	({								\

		u64 cptr = 0;						\

									\

		if ((set) & CPACR_ELx_FPEN)				\

		if ((set) & CPACR_EL1_FPEN)				\

			cptr |= CPTR_EL2_TFP;				\

		if ((set) & CPACR_ELx_ZEN)				\

		if ((set) & CPACR_EL1_ZEN)				\

			cptr |= CPTR_EL2_TZ;				\

		if ((set) & CPACR_ELx_SMEN)				\

		if ((set) & CPACR_EL1_SMEN)				\

			cptr |= CPTR_EL2_TSM;				\

		if ((clr) & CPACR_ELx_TTA)				\

		if ((clr) & CPACR_EL1_TTA)				\

			cptr |= CPTR_EL2_TTA;				\

		if ((clr) & CPTR_EL2_TAM)				\

			cptr |= CPTR_EL2_TAM;				\
@@ -576,13 +576,13 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 
	({								\

		u64 cptr = 0;						\

									\

		if ((clr) & CPACR_ELx_FPEN)				\

		if ((clr) & CPACR_EL1_FPEN)				\

			cptr |= CPTR_EL2_TFP;				\

		if ((clr) & CPACR_ELx_ZEN)				\

		if ((clr) & CPACR_EL1_ZEN)				\

			cptr |= CPTR_EL2_TZ;				\

		if ((clr) & CPACR_ELx_SMEN)				\

		if ((clr) & CPACR_EL1_SMEN)				\

			cptr |= CPTR_EL2_TSM;				\

		if ((set) & CPACR_ELx_TTA)				\

		if ((set) & CPACR_EL1_TTA)				\

			cptr |= CPTR_EL2_TTA;				\

		if ((set) & CPTR_EL2_TAM)				\

			cptr |= CPTR_EL2_TAM;				\
@@ -595,13 +595,13 @@ static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu) 
#define cpacr_clear_set(clr, set)					\

	do {								\

		BUILD_BUG_ON((set) & CPTR_VHE_EL2_RES0);		\

		BUILD_BUG_ON((clr) & CPACR_ELx_E0POE);			\

		__build_check_all_or_none((clr), CPACR_ELx_FPEN);	\

		__build_check_all_or_none((set), CPACR_ELx_FPEN);	\

		__build_check_all_or_none((clr), CPACR_ELx_ZEN);	\

		__build_check_all_or_none((set), CPACR_ELx_ZEN);	\

		__build_check_all_or_none((clr), CPACR_ELx_SMEN);	\

		__build_check_all_or_none((set), CPACR_ELx_SMEN);	\

		BUILD_BUG_ON((clr) & CPACR_EL1_E0POE);			\

		__build_check_all_or_none((clr), CPACR_EL1_FPEN);	\

		__build_check_all_or_none((set), CPACR_EL1_FPEN);	\

		__build_check_all_or_none((clr), CPACR_EL1_ZEN);	\

		__build_check_all_or_none((set), CPACR_EL1_ZEN);	\

		__build_check_all_or_none((clr), CPACR_EL1_SMEN);	\

		__build_check_all_or_none((set), CPACR_EL1_SMEN);	\

									\

		if (has_vhe() || has_hvhe())				\

			sysreg_clear_set(cpacr_el1, clr, set);		\
@@ -624,16 +624,16 @@ static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu) 
	u64 val;



	if (has_vhe()) {

		val = (CPACR_ELx_FPEN | CPACR_EL1_ZEN_EL1EN);

		val = (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN);

		if (cpus_have_final_cap(ARM64_SME))

			val |= CPACR_EL1_SMEN_EL1EN;

	} else if (has_hvhe()) {

		val = CPACR_ELx_FPEN;

		val = CPACR_EL1_FPEN;



		if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())

			val |= CPACR_ELx_ZEN;

			val |= CPACR_EL1_ZEN;

		if (cpus_have_final_cap(ARM64_SME))

			val |= CPACR_ELx_SMEN;

			val |= CPACR_EL1_SMEN;

	} else {

		val = CPTR_NVHE_EL2_RES1;
@@ -685,7 +685,7 @@ static inline bool ____cptr_xen_trap_enabled(const struct kvm_vcpu *vcpu, 
#define __guest_hyp_cptr_xen_trap_enabled(vcpu, xen)				\

	(!vcpu_has_nv(vcpu) ? false :						\

	 ____cptr_xen_trap_enabled(vcpu,					\

				   SYS_FIELD_GET(CPACR_ELx, xen,		\

				   SYS_FIELD_GET(CPACR_EL1, xen,		\

						 vcpu_sanitised_cptr_el2(vcpu))))



static inline bool guest_hyp_fpsimd_traps_enabled(const struct kvm_vcpu *vcpu)

arch/arm64/include/asm/kvm_nested.h

+4 −4
Original line number Diff line number Diff line
@@ -33,14 +33,14 @@ static inline u64 translate_tcr_el2_to_tcr_el1(u64 tcr) 


static inline u64 translate_cptr_el2_to_cpacr_el1(u64 cptr_el2)

{

	u64 cpacr_el1 = CPACR_ELx_RES1;

	u64 cpacr_el1 = CPACR_EL1_RES1;



	if (cptr_el2 & CPTR_EL2_TTA)

		cpacr_el1 |= CPACR_ELx_TTA;

		cpacr_el1 |= CPACR_EL1_TTA;

	if (!(cptr_el2 & CPTR_EL2_TFP))

		cpacr_el1 |= CPACR_ELx_FPEN;

		cpacr_el1 |= CPACR_EL1_FPEN;

	if (!(cptr_el2 & CPTR_EL2_TZ))

		cpacr_el1 |= CPACR_ELx_ZEN;

		cpacr_el1 |= CPACR_EL1_ZEN;



	cpacr_el1 |= cptr_el2 & (CPTR_EL2_TCPAC | CPTR_EL2_TAM);

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -2376,7 +2376,7 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 
static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)

{

	sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE);

	sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);

	sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE);

}

#endif