Commit e5ef4cd2 authored by Niravkumar L Rabara's avatar Niravkumar L Rabara Committed by Borislav Petkov (AMD)
Browse files

EDAC/altera: Use correct write width with the INTTEST register 



On the SoCFPGA platform, the INTTEST register supports only 16-bit writes.
A 32-bit write triggers an SError to the CPU so do 16-bit accesses only.

  [ bp: AI-massage the commit message. ]

Fixes: c7b4be8d ("EDAC, altera: Add Arria10 OCRAM ECC support")
Signed-off-by: default avatarNiravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: default avatarMatthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Acked-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Cc: stable@kernel.org
Link: https://lore.kernel.org/20250527145707.25458-1-matthew.gerlach@altera.com
parent ada1b043

drivers/edac/altera_edac.c

+3 −3
Original line number Diff line number Diff line
@@ -1746,9 +1746,9 @@ altr_edac_a10_device_trig(struct file *file, const char __user *user_buf, 


	local_irq_save(flags);

	if (trig_type == ALTR_UE_TRIGGER_CHAR)

		writel(priv->ue_set_mask, set_addr);

		writew(priv->ue_set_mask, set_addr);

	else

		writel(priv->ce_set_mask, set_addr);

		writew(priv->ce_set_mask, set_addr);



	/* Ensure the interrupt test bits are set */

	wmb();
@@ -1778,7 +1778,7 @@ altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf, 


	local_irq_save(flags);

	if (trig_type == ALTR_UE_TRIGGER_CHAR) {

		writel(priv->ue_set_mask, set_addr);

		writew(priv->ue_set_mask, set_addr);

	} else {

		/* Setup read/write of 4 bytes */

		writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);