Commit e62e1e94 authored by Lorenzo Pieralisi's avatar Lorenzo Pieralisi Committed by Marc Zyngier
Browse files

arm64: Add support for GICv5 GSB barriers 



The GICv5 architecture introduces two barriers instructions
(GSB SYS, GSB ACK) that are used to manage interrupt effects.

Rework macro used to emit the SB barrier instruction and implement
the GSB barriers on top of it.

Suggested-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-19-12e71f1b3528@kernel.org


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent ba1004f8

arch/arm64/include/asm/barrier.h

+3 −0
Original line number Diff line number Diff line
@@ -44,6 +44,9 @@ 
						 SB_BARRIER_INSN"nop\n",	\

						 ARM64_HAS_SB))



#define gsb_ack()	asm volatile(GSB_ACK_BARRIER_INSN : : : "memory")

#define gsb_sys()	asm volatile(GSB_SYS_BARRIER_INSN : : : "memory")



#ifdef CONFIG_ARM64_PSEUDO_NMI

#define pmr_sync()						\

	do {							\

arch/arm64/include/asm/sysreg.h

+8 −4
Original line number Diff line number Diff line
@@ -113,10 +113,14 @@ 
/* Register-based PAN access, for save/restore purposes */

#define SYS_PSTATE_PAN			sys_reg(3, 0, 4, 2, 3)



#define __SYS_BARRIER_INSN(CRm, op2, Rt) \

	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))



#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)

#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt)			\

	__emit_inst(0xd5000000					|	\

		    sys_insn((op0), (op1), (CRn), (CRm), (op2))	|	\

		    ((Rt) & 0x1f))



#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)

#define GSB_SYS_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31)

#define GSB_ACK_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31)



/* Data cache zero operations */

#define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)