drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactor (e6303950) · Commits · git / linux-net

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -174,6 +174,7 @@ static void dce_ipp_program_input_lut(
		struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);

		/* power on LUT memory */
		if (REG(DCFE_MEM_PWR_CTRL))
		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);

		/* enable all */
		@@ -199,6 +200,7 @@ static void dce_ipp_program_input_lut(
		}

		/* power off LUT memory */
		if (REG(DCFE_MEM_PWR_CTRL))
		REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);

		/* bypass prescale, enable legacy LUT */
		@@ -250,3 +252,9 @@ void dce_ipp_construct(
		ipp_dce->ipp_shift = ipp_shift;
		ipp_dce->ipp_mask = ipp_mask;
		}

		void dce_ipp_destroy(struct input_pixel_processor **ipp)
		{
		dm_free(TO_DCE_IPP(*ipp));
		*ipp = NULL;
		}

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h

+18 −6

Original line number	Diff line number	Diff line
		@@ -23,8 +23,8 @@
		*
		*/

		#ifndef _DCE_DCE_IPP_H_
		#define _DCE_DCE_IPP_H_
		#ifndef _DCE_IPP_H_
		#define _DCE_IPP_H_

		#include "ipp.h"

		@@ -46,7 +46,6 @@
		SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
		SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
		SRI(INPUT_GAMMA_CONTROL, DCP, id), \
		SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
		SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
		SRI(DC_LUT_RW_MODE, DCP, id), \
		SRI(DC_LUT_CONTROL, DCP, id), \
		@@ -54,6 +53,14 @@
		SRI(DC_LUT_SEQ_COLOR, DCP, id), \
		SRI(DEGAMMA_CONTROL, DCP, id)

		#define IPP_DCE100_REG_LIST_DCE_BASE(id) \
		IPP_COMMON_REG_LIST_DCE_BASE(id), \
		SRI(DCFE_MEM_PWR_CTRL, CRTC, id)

		#define IPP_DCE110_REG_LIST_DCE_BASE(id) \
		IPP_COMMON_REG_LIST_DCE_BASE(id), \
		SRI(DCFE_MEM_PWR_CTRL, DCFE, id)

		#define IPP_SF(reg_name, field_name, post_fix)\
		.field_name = reg_name ## __ ## field_name ## post_fix

		@@ -85,7 +92,6 @@
		IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
		IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
		IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
		IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
		IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
		IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
		IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
		@@ -97,7 +103,11 @@
		IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
		IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)

		#define IPP_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
		#define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
		IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
		IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)

		#define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \
		IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
		IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \
		IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \
		@@ -223,4 +233,6 @@ void dce_ipp_construct(struct dce_ipp *ipp_dce,
		const struct dce_ipp_shift *ipp_shift,
		const struct dce_ipp_mask *ipp_mask);

		#endif /* _DCE_DCE_IPP_H_ */
		void dce_ipp_destroy(struct input_pixel_processor **ipp);

		#endif /* _DCE_IPP_H_ */

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+33 −40

Original line number	Diff line number	Diff line
		@@ -37,7 +37,7 @@
		#include "dce/dce_stream_encoder.h"
		#include "dce110/dce110_mem_input.h"
		#include "dce110/dce110_mem_input_v.h"
		#include "dce110/dce110_ipp.h"
		#include "dce/dce_ipp.h"
		#include "dce/dce_transform.h"
		#include "dce/dce_opp.h"
		#include "dce/dce_clocks.h"
		@@ -168,30 +168,6 @@ static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {
		}
		};


		static const struct dce110_ipp_reg_offsets dce100_ipp_reg_offsets[] = {
		{
		.dcp_offset = (mmDCP0_CUR_CONTROL - mmCUR_CONTROL),
		},
		{
		.dcp_offset = (mmDCP1_CUR_CONTROL - mmCUR_CONTROL),
		},
		{
		.dcp_offset = (mmDCP2_CUR_CONTROL - mmCUR_CONTROL),
		},
		{
		.dcp_offset = (mmDCP3_CUR_CONTROL - mmCUR_CONTROL),
		},
		{
		.dcp_offset = (mmDCP4_CUR_CONTROL - mmCUR_CONTROL),
		},
		{
		.dcp_offset = (mmDCP5_CUR_CONTROL - mmCUR_CONTROL),
		}
		};



		/* set register offset */
		#define SR(reg_name)\
		.reg_name = mm ## reg_name
		@@ -213,6 +189,28 @@ static const struct dce_disp_clk_mask disp_clk_mask = {
		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
		};

		#define ipp_regs(id)\
		[id] = {\
		IPP_DCE100_REG_LIST_DCE_BASE(id)\
		}

		static const struct dce_ipp_registers ipp_regs[] = {
		ipp_regs(0),
		ipp_regs(1),
		ipp_regs(2),
		ipp_regs(3),
		ipp_regs(4),
		ipp_regs(5)
		};

		static const struct dce_ipp_shift ipp_shift = {
		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
		};

		static const struct dce_ipp_mask ipp_mask = {
		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
		};

		#define transform_regs(id)\
		[id] = {\
		XFM_COMMON_REG_LIST_DCE100(id)\
		@@ -563,22 +561,18 @@ static struct transform *dce100_transform_create(
		}

		static struct input_pixel_processor *dce100_ipp_create(
		struct dc_context *ctx,
		uint32_t inst,
		const struct dce110_ipp_reg_offsets *offsets)
		struct dc_context *ctx, uint32_t inst)
		{
		struct dce110_ipp *ipp =
		dm_alloc(sizeof(struct dce110_ipp));
		struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));

		if (!ipp)
		if (!ipp) {
		BREAK_TO_DEBUGGER();
		return NULL;
		}

		if (dce110_ipp_construct(ipp, ctx, inst, offsets))
		dce_ipp_construct(ipp, ctx, inst,
		&ipp_regs[inst], &ipp_shift, &ipp_mask);
		return &ipp->base;

		BREAK_TO_DEBUGGER();
		dm_free(ipp);
		return NULL;
		}

		static const struct encoder_feature_support link_enc_feature = {
		@@ -674,7 +668,7 @@ static void destruct(struct dce110_resource_pool *pool)
		dce100_transform_destroy(&pool->base.transforms[i]);

		if (pool->base.ipps[i] != NULL)
		dce110_ipp_destroy(&pool->base.ipps[i]);
		dce_ipp_destroy(&pool->base.ipps[i]);

		if (pool->base.mis[i] != NULL) {
		dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));
		@@ -1005,8 +999,7 @@ static bool construct(
		goto res_create_fail;
		}

		pool->base.ipps[i] = dce100_ipp_create(ctx, i,
		&dce100_ipp_reg_offsets[i]);
		pool->base.ipps[i] = dce100_ipp_create(ctx, i);
		if (pool->base.ipps[i] == NULL) {
		BREAK_TO_DEBUGGER();
		dm_error(

drivers/gpu/drm/amd/display/dc/dce110/Makefile

+1 −3

Original line number	Diff line number	Diff line
		@@ -2,9 +2,7 @@
		# Makefile for the 'controller' sub-component of DAL.
		# It provides the control and status of HW CRTC block.

		DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
		dce110_ipp_gamma.o \
		dce110_timing_generator.o \
		DCE110 = dce110_timing_generator.o \
		dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
		dce110_resource.o \
		dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \

drivers/gpu/drm/amd/display/dc/dce110/dce110_ipp.c

deleted100644 → 0

+0 −63

Original line number	Diff line number	Diff line
		/*
		* Copyright 2012-15 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		* Authors: AMD
		*
		*/

		#include "dm_services.h"
		#include "include/logger_interface.h"

		#include "dce/dce_11_0_d.h"
		#include "dce/dce_11_0_sh_mask.h"

		#include "dce110_ipp.h"

		static const struct ipp_funcs funcs = {
		.ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes,
		.ipp_cursor_set_position = dce110_ipp_cursor_set_position,
		.ipp_program_prescale = dce110_ipp_program_prescale,
		.ipp_program_input_lut = dce110_ipp_program_input_lut,
		.ipp_set_degamma = dce110_ipp_set_degamma,
		};

		bool dce110_ipp_construct(
		struct dce110_ipp* ipp,
		struct dc_context *ctx,
		uint32_t inst,
		const struct dce110_ipp_reg_offsets *offset)
		{
		ipp->base.ctx = ctx;

		ipp->base.inst = inst;

		ipp->offsets = *offset;

		ipp->base.funcs = &funcs;

		return true;
		}

		void dce110_ipp_destroy(struct input_pixel_processor **ipp)
		{
		dm_free(TO_DCE110_IPP(*ipp));
		*ipp = NULL;
		}