Commit e63265f9 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'intel-wired-lan-driver-updates-2025-03-10-ice-ixgbe' 

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2025-03-10 (ice, ixgbe)

For ice:

Paul adds generic checksum support for E830 devices.

Karol refactors PTP code related to E825C; simplifying PHY register info
struct, utilizing GENMASK, removing unused defines, etc.

For ixgbe:

Piotr adds PTP support for E610 devices.

Jedrzej adds reporting when overheating is detected on E610 devices.

The following are changes since commit 8ef890df:
  net: move misc netdev_lock flavors to a separate header
and are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 100GbE
====================

Link: https://patch.msgid.link/20250310174502.3708121-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 50698b29 affead2d

drivers/net/ethernet/intel/ice/ice.h

+1 −0
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ enum ice_feature { 
	ICE_F_SMA_CTRL,

	ICE_F_CGU,

	ICE_F_GNSS,

	ICE_F_GCS,

	ICE_F_ROCE_LAG,

	ICE_F_SRIOV_LAG,

	ICE_F_MBX_LIMIT,

drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h

+7 −2
Original line number Diff line number Diff line
@@ -229,7 +229,7 @@ struct ice_32b_rx_flex_desc_nic { 
	__le16 status_error1;

	u8 flexi_flags2;

	u8 ts_low;

	__le16 l2tag2_1st;

	__le16 raw_csum;

	__le16 l2tag2_2nd;



	/* Qword 3 */
@@ -478,10 +478,15 @@ enum ice_tx_desc_len_fields { 
struct ice_tx_ctx_desc {

	__le32 tunneling_params;

	__le16 l2tag2;

	__le16 rsvd;

	__le16 gcs;

	__le64 qw1;

};



#define ICE_TX_GCS_DESC_START_M		GENMASK(7, 0)

#define ICE_TX_GCS_DESC_OFFSET_M	GENMASK(11, 8)

#define ICE_TX_GCS_DESC_TYPE_M		GENMASK(14, 12)

#define ICE_TX_GCS_DESC_CSUM_PSH	1



#define ICE_TXD_CTX_QW1_CMD_S	4

#define ICE_TXD_CTX_QW1_CMD_M	(0x7FUL << ICE_TXD_CTX_QW1_CMD_S)

drivers/net/ethernet/intel/ice/ice_lib.c

+7 −1
Original line number Diff line number Diff line
@@ -1431,6 +1431,10 @@ static int ice_vsi_alloc_rings(struct ice_vsi *vsi) 
		ring->dev = dev;

		ring->count = vsi->num_rx_desc;

		ring->cached_phctime = pf->ptp.cached_phc_time;



		if (ice_is_feature_supported(pf, ICE_F_GCS))

			ring->flags |= ICE_RX_FLAGS_RING_GCS;



		WRITE_ONCE(vsi->rx_rings[i], ring);

	}
@@ -3899,8 +3903,10 @@ void ice_init_feature_support(struct ice_pf *pf) 
		break;

	}



	if (pf->hw.mac_type == ICE_MAC_E830)

	if (pf->hw.mac_type == ICE_MAC_E830) {

		ice_set_feature_support(pf, ICE_F_MBX_LIMIT);

		ice_set_feature_support(pf, ICE_F_GCS);

	}

}



/**

drivers/net/ethernet/intel/ice/ice_main.c

+18 −0
Original line number Diff line number Diff line
@@ -3634,6 +3634,12 @@ void ice_set_netdev_features(struct net_device *netdev) 
	/* Allow core to manage IRQs affinity */

	netif_set_affinity_auto(netdev);



	/* Mutual exclusivity for TSO and GCS is enforced by the set features

	 * ndo callback.

	 */

	if (ice_is_feature_supported(pf, ICE_F_GCS))

		netdev->hw_features |= NETIF_F_HW_CSUM;



	netif_set_tso_max_size(netdev, ICE_MAX_TSO_SIZE);

}
@@ -6549,6 +6555,18 @@ ice_set_features(struct net_device *netdev, netdev_features_t features) 
	if (changed & NETIF_F_LOOPBACK)

		ret = ice_set_loopback(vsi, !!(features & NETIF_F_LOOPBACK));



	/* Due to E830 hardware limitations, TSO (NETIF_F_ALL_TSO) with GCS

	 * (NETIF_F_HW_CSUM) is not supported.

	 */

	if (ice_is_feature_supported(pf, ICE_F_GCS) &&

	    ((features & NETIF_F_HW_CSUM) && (features & NETIF_F_ALL_TSO))) {

		if (netdev->features & NETIF_F_HW_CSUM)

			dev_err(ice_pf_to_dev(pf), "To enable TSO, you must first disable HW checksum.\n");

		else

			dev_err(ice_pf_to_dev(pf), "To enable HW checksum, you must first disable TSO.\n");

		return -EIO;

	}



	return ret;

}

drivers/net/ethernet/intel/ice/ice_ptp_consts.h

+15 −60
Original line number Diff line number Diff line
@@ -10,70 +10,25 @@ 
/* Constants defined for the PTP 1588 clock hardware. */



const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {

	/* ETH56G_PHY_REG_PTP */

	{

		/* base_addr */

		{

			0x092000,

			0x126000,

			0x1BA000,

			0x24E000,

			0x2E2000,

		},

		/* step */

		0x98,

	},

	/* ETH56G_PHY_MEM_PTP */

	{

		/* base_addr */

		{

			0x093000,

			0x127000,

			0x1BB000,

			0x24F000,

			0x2E3000,

		},

		/* step */

		0x200,

	[ETH56G_PHY_REG_PTP] = {

		.base_addr = 0x092000,

		.step = 0x98,

	},

	/* ETH56G_PHY_REG_XPCS */

	{

		/* base_addr */

		{

			0x000000,

			0x009400,

			0x128000,

			0x1BC000,

			0x250000,

	[ETH56G_PHY_MEM_PTP] = {

		.base_addr = 0x093000,

		.step = 0x200,

	},

		/* step */

		0x21000,

	[ETH56G_PHY_REG_XPCS] = {

		.base_addr = 0x000000,

		.step = 0x21000,

	},

	/* ETH56G_PHY_REG_MAC */

	{

		/* base_addr */

		{

			0x085000,

			0x119000,

			0x1AD000,

			0x241000,

			0x2D5000,

	[ETH56G_PHY_REG_MAC] = {

		.base_addr = 0x085000,

		.step = 0x1000,

	},

		/* step */

		0x1000,

	},

	/* ETH56G_PHY_REG_GPCS */

	{

		/* base_addr */

		{

			0x084000,

			0x118000,

			0x1AC000,

			0x240000,

			0x2D4000,

		},

		/* step */

		0x400,

	[ETH56G_PHY_REG_GPCS] = {

		.base_addr = 0x084000,

		.step = 0x400,

	},

};