Commit e63e9f8b authored by Reza Amini's avatar Reza Amini Committed by Alex Deucher
Browse files

drm/amd/display: Fixing hubp programming of 3dlut fast load 



[why]
HUBP needs to know the size of the lut's destination in MPC.
This is currently defaulted to 17, and needs to be set for specific
lut size.

[how]
Define and apply the missing hubp field. Taking this opportunity
to consolidate the programming of 3dlut into a hubp and mpc function.

Reviewed-by: default avatarKrunoslav Kovac <krunoslav.kovac@amd.com>
Signed-off-by: default avatarReza Amini <reza.amini@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3df95751

drivers/gpu/drm/amd/display/dc/dc.h

+26 −0
Original line number Diff line number Diff line
@@ -1311,6 +1311,32 @@ union dc_3dlut_state { 
};





#define MATRIX_9C__DIM_128_ALIGNED_LEN   16 // 9+8 :  9 * 8 +  7 * 8 = 72  + 56  = 128 % 128 = 0

#define MATRIX_17C__DIM_128_ALIGNED_LEN  32 //17+15:  17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0

#define MATRIX_33C__DIM_128_ALIGNED_LEN  64 //17+47:  17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0



struct lut_rgb {

	uint16_t b;

	uint16_t g;

	uint16_t r;

	uint16_t padding;

};



//this structure maps directly to how the lut will read it from memory

struct lut_mem_mapping {

	union {

		//NATIVE MODE 1, 2

		//RGB layout          [b][g][r]      //red  is 128 byte aligned

		//BGR layout          [r][g][b]      //blue is 128 byte aligned

		struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN];

		struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN];



		//TRANSFORMED

		uint16_t linear_rgb[(33*33*33*4/128+1)*128];

	};

	uint16_t size;

};



struct dc_rmcm_3dlut {

	bool isInUse;

	const struct dc_stream_state *stream;

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

+1 −0
Original line number Diff line number Diff line
@@ -671,6 +671,7 @@ struct dcn_fl_regs_st { 
	uint32_t lut_done;

	uint32_t lut_addr_mode;

	uint32_t lut_width;

	uint32_t lut_mpc_width;

	uint32_t lut_tmz;

	uint32_t lut_crossbar_sel_r;

	uint32_t lut_crossbar_sel_g;

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

+1 −0
Original line number Diff line number Diff line
@@ -264,6 +264,7 @@ 
	type HUBP_3DLUT_DONE;\

	type HUBP_3DLUT_ADDRESSING_MODE;\

	type HUBP_3DLUT_WIDTH;\

	type HUBP_3DLUT_MPC_WIDTH;\

	type HUBP_3DLUT_TMZ;\

	type HUBP_3DLUT_CROSSBAR_SELECT_Y_G;\

	type HUBP_3DLUT_CROSSBAR_SELECT_CB_B;\

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

+38 −0
Original line number Diff line number Diff line
@@ -127,6 +127,43 @@ void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_forma 
	REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format);

}



void hubp401_program_3dlut_fl_config(

	struct hubp *hubp,

	struct hubp_fl_3dlut_config *cfg)

{

	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);



	uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1};

	uint32_t width = {cfg->width};



	if (cfg->layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR)

		width = (cfg->width == 17) ? 4916 : 35940;



	REG_UPDATE_2(_3DLUT_FL_CONFIG,

		HUBP0_3DLUT_FL_MODE, cfg->mode,

		HUBP0_3DLUT_FL_FORMAT, cfg->format);



	REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE,

		HUBP0_3DLUT_FL_BIAS, cfg->bias,

		HUBP0_3DLUT_FL_SCALE, cfg->scale);



	REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH,

		HUBP_3DLUT_ADDRESS_HIGH, cfg->address.lut3d.addr.high_part);

	REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW,

		HUBP_3DLUT_ADDRESS_LOW, cfg->address.lut3d.addr.low_part);



	//cross bar

	REG_UPDATE_8(HUBP_3DLUT_CONTROL,

		HUBP_3DLUT_MPC_WIDTH, mpc_width,

		HUBP_3DLUT_WIDTH, width,

		HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg->crossbar_bit_slice_cr_r,

		HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg->crossbar_bit_slice_y_g,

		HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg->crossbar_bit_slice_cb_b,

		HUBP_3DLUT_ADDRESSING_MODE, cfg->addr_mode,

		HUBP_3DLUT_TMZ, cfg->protection_bits,

		HUBP_3DLUT_ENABLE, cfg->enabled ? 1 : 0);

}



void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor)

{

	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
@@ -1033,6 +1070,7 @@ static struct hubp_funcs dcn401_hubp_funcs = { 
	.hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar,

	.hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done,

	.hubp_clear_tiling = hubp401_clear_tiling,

	.hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config,

};



bool hubp401_construct(

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

+4 −0
Original line number Diff line number Diff line
@@ -349,6 +349,10 @@ void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_forma 


void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode);



void hubp401_program_3dlut_fl_config(

	struct hubp *hubp,

	struct hubp_fl_3dlut_config *cfg);



void hubp401_clear_tiling(struct hubp *hubp);



void hubp401_vready_at_or_After_vsync(struct hubp *hubp,