Commit e67e40cf authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

ARM: dts: imx7-tqma7/mba7: convert fsl,pins to uint32-matrix 



make dtbs_check does not warn about this anymore, but bindings mandate
a uint32-matrix.

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 6613476e

arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi

+110 −132
Original line number Diff line number Diff line
@@ -334,213 +334,191 @@ &iomuxc { 
	pinctrl-0 = <&pinctrl_hog_mba7_1>;



	pinctrl_ecspi1: ecspi1grp {

		fsl,pins = <

			MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO		0x7c

			MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI		0x74

			MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK		0x74

			MX7D_PAD_UART1_RX_DATA__GPIO4_IO0		0x74

			MX7D_PAD_UART1_TX_DATA__GPIO4_IO1		0x74

			MX7D_PAD_UART2_RX_DATA__GPIO4_IO2		0x74

		>;

		fsl,pins =

			<MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO		0x7c>,

			<MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI		0x74>,

			<MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK		0x74>,

			<MX7D_PAD_UART1_RX_DATA__GPIO4_IO0		0x74>,

			<MX7D_PAD_UART1_TX_DATA__GPIO4_IO1		0x74>,

			<MX7D_PAD_UART2_RX_DATA__GPIO4_IO2		0x74>;

	};



	pinctrl_ecspi2: ecspi2grp {

		fsl,pins = <

			MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO		0x7c

			MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI		0x74

			MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK		0x74

			MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0			0x74

		>;

		fsl,pins =

			<MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO		0x7c>,

			<MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI		0x74>,

			<MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK		0x74>,

			<MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0		0x74>;

	};



	pinctrl_enet1: enet1grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x02

			MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x00

			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x71

			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x71

			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x71

			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x71

			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x71

			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x71

			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x79

			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x79

			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x79

			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x79

			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x79

			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x79

		fsl,pins =

			<MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x02>,

			<MX7D_PAD_GPIO1_IO11__ENET1_MDC				0x00>,

			<MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC		0x71>,

			<MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0		0x71>,

			<MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1		0x71>,

			<MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2		0x71>,

			<MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3		0x71>,

			<MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x71>,

			<MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC		0x79>,

			<MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0		0x79>,

			<MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1		0x79>,

			<MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2		0x79>,

			<MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3		0x79>,

			<MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x79>,

			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */

			MX7D_PAD_ENET1_COL__GPIO7_IO15		0x40000070

			<MX7D_PAD_ENET1_COL__GPIO7_IO15				0x40000070>,

			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */

			MX7D_PAD_GPIO1_IO09__GPIO1_IO9		0x40000078

		>;

			<MX7D_PAD_GPIO1_IO09__GPIO1_IO9				0x40000078>;

	};



	pinctrl_flexcan1: flexcan1grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x5a

			MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x52

		>;

		fsl,pins =

			<MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x5a>,

			<MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x52>;

	};



	pinctrl_flexcan2: flexcan2grp {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x5a

			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x52

		>;

		fsl,pins =

			<MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x5a>,

			<MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x52>;

	};



	pinctrl_hog_mba7_1: hogmba71grp {

		fsl,pins = <

		fsl,pins =

			/* Limitation: WDOG2_B / WDOG2_RESET not usable */

			MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13	0x4000007c

			MX7D_PAD_ENET1_CRS__GPIO7_IO14		0x40000074

			<MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13	0x4000007c>,

			<MX7D_PAD_ENET1_CRS__GPIO7_IO14		0x40000074>,

			/* #BOOT_EN */

			MX7D_PAD_UART2_TX_DATA__GPIO4_IO3	0x40000010

		>;

			<MX7D_PAD_UART2_TX_DATA__GPIO4_IO3	0x40000010>;

	};



	pinctrl_i2c2: i2c2grp {

		fsl,pins = <

			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x40000078

			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x40000078

		>;

		fsl,pins =

			<MX7D_PAD_I2C2_SCL__I2C2_SCL		0x40000078>,

			<MX7D_PAD_I2C2_SDA__I2C2_SDA		0x40000078>;

	};



	pinctrl_i2c3: i2c3grp {

		fsl,pins = <

			MX7D_PAD_I2C3_SCL__I2C3_SCL		0x40000078

			MX7D_PAD_I2C3_SDA__I2C3_SDA		0x40000078

		>;

		fsl,pins =

			<MX7D_PAD_I2C3_SCL__I2C3_SCL		0x40000078>,

			<MX7D_PAD_I2C3_SDA__I2C3_SDA		0x40000078>;

	};



	pinctrl_pca9555: pca95550grp {

		fsl,pins = <

			MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12	0x78

		>;

		fsl,pins =

			<MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12	0x78>;

	};



	pinctrl_sai1: sai1grp {

		fsl,pins = <

			MX7D_PAD_SAI1_MCLK__SAI1_MCLK		0x11

			MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK	0x1c

			MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0	0x1c

			MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC	0x1c

		fsl,pins =

			<MX7D_PAD_SAI1_MCLK__SAI1_MCLK		0x11>,

			<MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK	0x1c>,

			<MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0	0x1c>,

			<MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC	0x1c>,



			MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1c

			MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x14

			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x14

		>;

			<MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1c>,

			<MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x14>,

			<MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x14>;

	};



	pinctrl_uart3: uart3grp {

		fsl,pins = <

			MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x7e

			MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x76

			MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x76

			MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x7e

		>;

		fsl,pins =

			<MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x7e>,

			<MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x76>,

			<MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x76>,

			<MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x7e>;

	};



	pinctrl_uart4: uart4grp {

		fsl,pins = <

			MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX	0x7e

			MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX	0x76

			MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS	0x76

			MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS	0x7e

		>;

		fsl,pins =

			<MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX	0x7e>,

			<MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX	0x76>,

			<MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS	0x76>,

			<MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS	0x7e>;

	};



	pinctrl_uart5: uart5grp {

		fsl,pins = <

			MX7D_PAD_I2C4_SCL__UART5_DCE_RX		0x7e

			MX7D_PAD_I2C4_SDA__UART5_DCE_TX		0x76

		>;

		fsl,pins =

			<MX7D_PAD_I2C4_SCL__UART5_DCE_RX	0x7e>,

			<MX7D_PAD_I2C4_SDA__UART5_DCE_TX	0x76>;

	};



	pinctrl_uart6: uart6grp {

		fsl,pins = <

			MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x7d

			MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x75

			MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x75

			MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x7d

		>;

		fsl,pins =

			<MX7D_PAD_EPDC_DATA08__UART6_DCE_RX	0x7d>,

			<MX7D_PAD_EPDC_DATA09__UART6_DCE_TX	0x75>,

			<MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS	0x75>,

			<MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS	0x7d>;

	};



	pinctrl_uart7: uart7grp {

		fsl,pins = <

			MX7D_PAD_EPDC_DATA12__UART7_DCE_RX	0x7e

			MX7D_PAD_EPDC_DATA13__UART7_DCE_TX	0x76

			MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS	0x76

		fsl,pins =

			<MX7D_PAD_EPDC_DATA12__UART7_DCE_RX	0x7e>,

			<MX7D_PAD_EPDC_DATA13__UART7_DCE_TX	0x76>,

			<MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS	0x76>,

			/* Limitation: RTS is not connected */

			MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS	0x7e

		>;

			<MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS	0x7e>;

	};



	pinctrl_usdhc1_gpio: usdhc1grp_gpio {

		fsl,pins = <

		fsl,pins =

			/* WP */

			MX7D_PAD_SD1_WP__GPIO5_IO1		0x7c

			<MX7D_PAD_SD1_WP__GPIO5_IO1		0x7c>,

			/* CD */

			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x7c

			<MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x7c>,

			/* VSELECT */

			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59

		>;

			<MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59>;

	};



	pinctrl_usdhc1: usdhc1grp {

		fsl,pins = <

			MX7D_PAD_SD1_CMD__SD1_CMD		0x5e

			MX7D_PAD_SD1_CLK__SD1_CLK		0x57

			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5e

			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5e

			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5e

			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5e

		>;

		fsl,pins =

			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5e>,

			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,

			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5e>,

			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5e>,

			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5e>,

			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5e>;

	};



	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {

		fsl,pins = <

			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a

			MX7D_PAD_SD1_CLK__SD1_CLK		0x57

			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a

			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a

			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a

			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a

		>;

		fsl,pins =

			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5a>,

			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,

			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a>,

			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a>,

			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a>,

			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a>;

	};



	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {

		fsl,pins = <

			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b

			MX7D_PAD_SD1_CLK__SD1_CLK		0x57

			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b

			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b

			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b

			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b

		>;

		fsl,pins =

			<MX7D_PAD_SD1_CMD__SD1_CMD		0x5b>,

			<MX7D_PAD_SD1_CLK__SD1_CLK		0x57>,

			<MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b>,

			<MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b>,

			<MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b>,

			<MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b>;

	};

};



&iomuxc_lpsr {

	pinctrl_pwm1: pwm1grp {

		fsl,pins = <

		fsl,pins =

			/* LCD_CONTRAST */

			MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT	0x50

		>;

			<MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT	0x50>;

	};



	pinctrl_usbotg1: usbotg1grp {

		fsl,pins = <

			MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC	0x5c

			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x59

		>;

		fsl,pins =

			<MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC	0x5c>,

			<MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x59>;

	};



	pinctrl_wdog1: wdog1grp {

		fsl,pins = <

			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x30

		>;

		fsl,pins =

			<MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x30>;

	};

};

arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi

+53 −61
Original line number Diff line number Diff line
@@ -163,91 +163,83 @@ ds1339: rtc@68 { 


&iomuxc {

	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX7D_PAD_I2C1_SDA__I2C1_SDA	0x40000078

			MX7D_PAD_I2C1_SCL__I2C1_SCL	0x40000078

		>;

		fsl,pins =

			<MX7D_PAD_I2C1_SDA__I2C1_SDA	0x40000078>,

			<MX7D_PAD_I2C1_SCL__I2C1_SCL	0x40000078>;

	};



	pinctrl_pmic1: pmic1grp {

		fsl,pins = <

			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x4000005C

		>;

		fsl,pins =

			<MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x4000005C>;

	};



	pinctrl_qspi: qspigrp {

		fsl,pins = <

			MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0	0x5A

			MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1	0x5A

			MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2	0x5A

			MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3	0x5A

			MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK	0x11

			MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B	0x54

			MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B	0x54

		>;

		fsl,pins =

			<MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0	0x5A>,

			<MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1	0x5A>,

			<MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2	0x5A>,

			<MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3	0x5A>,

			<MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK	0x11>,

			<MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B	0x54>,

			<MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B	0x54>;

	};



	pinctrl_qspi_reset: qspi_resetgrp {

		fsl,pins = <

		fsl,pins =

			/* #QSPI_RESET */

			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x52

		>;

			<MX7D_PAD_EPDC_DATA04__GPIO2_IO4	0x52>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <

			MX7D_PAD_SD3_CMD__SD3_CMD		0x59

			MX7D_PAD_SD3_CLK__SD3_CLK		0x56

			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59

			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59

			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59

			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59

			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59

			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59

			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59

			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59

			MX7D_PAD_SD3_STROBE__SD3_STROBE		0x19

		>;

		fsl,pins =

			<MX7D_PAD_SD3_CMD__SD3_CMD		0x59>,

			<MX7D_PAD_SD3_CLK__SD3_CLK		0x56>,

			<MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59>,

			<MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59>,

			<MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59>,

			<MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59>,

			<MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59>,

			<MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59>,

			<MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59>,

			<MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59>,

			<MX7D_PAD_SD3_STROBE__SD3_STROBE	0x19>;

	};



	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {

		fsl,pins = <

			MX7D_PAD_SD3_CMD__SD3_CMD               0x5a

			MX7D_PAD_SD3_CLK__SD3_CLK               0x51

			MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a

			MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a

			MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a

			MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a

			MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a

			MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a

			MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a

			MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a

			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a

		>;

		fsl,pins =

			<MX7D_PAD_SD3_CMD__SD3_CMD               0x5a>,

			<MX7D_PAD_SD3_CLK__SD3_CLK               0x51>,

			<MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a>,

			<MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a>,

			<MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a>,

			<MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a>,

			<MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a>,

			<MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a>,

			<MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a>,

			<MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a>,

			<MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a>;

	};



	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {

		fsl,pins = <

			MX7D_PAD_SD3_CMD__SD3_CMD               0x5b

			MX7D_PAD_SD3_CLK__SD3_CLK               0x51

			MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b

			MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b

			MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b

			MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b

			MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b

			MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b

			MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b

			MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b

			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b

		>;

		fsl,pins =

			<MX7D_PAD_SD3_CMD__SD3_CMD               0x5b>,

			<MX7D_PAD_SD3_CLK__SD3_CLK               0x51>,

			<MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b>,

			<MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b>,

			<MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b>,

			<MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b>,

			<MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b>,

			<MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b>,

			<MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b>,

			<MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b>,

			<MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b>;

	};

};



&iomuxc_lpsr {

	pinctrl_wdog1: wdog1grp {

		fsl,pins = <

			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x30

		>;

		fsl,pins =

			<MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x30>;

	};

};

arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts

+24 −27
Original line number Diff line number Diff line
@@ -48,46 +48,43 @@ &iomuxc { 
	pinctrl-0 = <&pinctrl_hog_mba7_1>;



	pinctrl_enet2: enet2grp {

		fsl,pins = <

			MX7D_PAD_SD2_CD_B__ENET2_MDIO			0x02

			MX7D_PAD_SD2_WP__ENET2_MDC			0x00

			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x71

			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x71

			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x71

			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x71

			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x71

			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x71

			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x79

			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x79

			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x79

			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x79

			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x79

			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x79

		fsl,pins =

			<MX7D_PAD_SD2_CD_B__ENET2_MDIO			0x02>,

			<MX7D_PAD_SD2_WP__ENET2_MDC			0x00>,

			<MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x71>,

			<MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x71>,

			<MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x71>,

			<MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x71>,

			<MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x71>,

			<MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x71>,

			<MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x79>,

			<MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x79>,

			<MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x79>,

			<MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x79>,

			<MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x79>,

			<MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x79>,

			/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */

			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x40000070

			<MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x40000070>,

			/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */

			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x40000078

		>;

			<MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x40000078>;

	};



	pinctrl_pcie: pciegrp {

		fsl,pins = <

		fsl,pins =

			/* #pcie_wake */

			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30		0x70

			<MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30		0x70>,

			/* #pcie_rst */

			MX7D_PAD_SD2_CLK__GPIO5_IO12			0x70

			<MX7D_PAD_SD2_CLK__GPIO5_IO12			0x70>,

			/* #pcie_dis */

			MX7D_PAD_EPDC_BDR1__GPIO2_IO29			0x70

		>;

			<MX7D_PAD_EPDC_BDR1__GPIO2_IO29			0x70>;

	};

};



&iomuxc_lpsr {

	pinctrl_usbotg2: usbotg2grp {

		fsl,pins = <

			MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC	0x5c

			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x59

		>;

		fsl,pins =

			<MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC	0x5c>,

			<MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x59>;

	};

};