Commit e6810000 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a09g077: Propagate rate changes through mux parents 



Enable CLK_SET_RATE_PARENT for mux clocks so that rate changes can properly
propagate to their parent clocks. Several clocks in the R9A09G077 CPG tree
depend on upstream PLL or divider outputs being recalculated when a child
requests a new frequency. Without this flag, rate adjustments stop at the
mux layer, leaving parent rates unchanged and preventing the clock tree
from converging on the intended values.

Set the flag in DEF_MUX to ensure that parent clocks participate in rate
negotiation, which is required for correct operation of the display and
peripheral related clocks being added for RZ/T2H support.

Fixes: 065fe720 ("clk: renesas: Add support for R9A09G077 SoC")
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251121090853.5220-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent ec74d201

drivers/clk/renesas/r9a09g077-cpg.c

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ enum rzt2h_clk_types { 
#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \

	DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \

		 .parent_names = _parent_names, .num_parents = _num_parents, \

		 .flag = 0, .mux_flags = _mux_flags)

		 .flag = CLK_SET_RATE_PARENT, .mux_flags = _mux_flags)

#define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \

	DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf = _conf, \

		 .parent = _parent, .dtable = _dtable, .flag = 0)