Commit e6c0e853 authored by Ovidiu Bunea's avatar Ovidiu Bunea Committed by Alex Deucher
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drm/amd/display: Move all DCCG RCG into HWSS root_clock_control 



[why & how]
Enabling/disabling DCCG RCG should be done as a last-level step when
enabling/disable blocks. This is handled by HWSS root_clock_control
already during optimize_bandwidth.
However, dccg35_dpp_root_clock_control was missing the RCG enable
call on the disable path.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarOvidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d745900b

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

+2 −3
Original line number Diff line number Diff line
@@ -1184,8 +1184,7 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, 
		dcn35_set_dppclk_enable(dccg, dpp_inst, true);

	} else {

		dcn35_set_dppclk_enable(dccg, dpp_inst, false);

		/*we have this in hwss: disable_plane*/

		//dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

		dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

	}

	udelay(10);

	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
@@ -1695,7 +1694,7 @@ static void dccg35_dpp_root_clock_control( 
			  DPPCLK0_DTO_PHASE, 0,

			  DPPCLK0_DTO_MODULO, 1);

		/*we have this in hwss: disable_plane*/

		//dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

		dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

	}



	// wait for clock to fully ramp

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+0 −5
Original line number Diff line number Diff line
@@ -817,8 +817,6 @@ void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 
			       struct dc_state *context)

{

	struct dpp *dpp = pipe_ctx->plane_res.dpp;

	struct dccg *dccg = dc->res_pool->dccg;





	/* enable DCFCLK current DCHUB */

	pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
@@ -826,7 +824,6 @@ void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 
	/* initialize HUBP on power up */

	pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);

	/*make sure DPPCLK is on*/

	dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true);

	dpp->funcs->dpp_dppclk_control(dpp, false, true);

	/* make sure OPP_PIPE_CLOCK_EN = 1 */

	pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
@@ -860,7 +857,6 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 
{

	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	struct dpp *dpp = pipe_ctx->plane_res.dpp;

	struct dccg *dccg = dc->res_pool->dccg;





	dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
@@ -879,7 +875,6 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 
	hubp->funcs->hubp_clk_cntl(hubp, false);



	dpp->funcs->dpp_dppclk_control(dpp, false, false);

	dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false);



	hubp->power_gated = true;