Unverified Commit e72c4333 authored by Xiao Wang's avatar Xiao Wang Committed by Palmer Dabbelt
Browse files

riscv: Rearrange hwcap.h and cpufeature.h 



Now hwcap.h and cpufeature.h are mutually including each other, and most of
the variable/API declarations in hwcap.h are implemented in cpufeature.c,
so, it's better to move them into cpufeature.h and leave only macros for
ISA extension logical IDs in hwcap.h.

BTW, the riscv_isa_extension_mask macro is not used now, so this patch
removes it.

Suggested-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarXiao Wang <xiao.w.wang@intel.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20231031064553.2319688-2-xiao.w.wang@intel.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 68444b93

arch/riscv/include/asm/cpufeature.h

+83 −0
Original line number Diff line number Diff line
@@ -7,7 +7,10 @@ 
#define _ASM_CPUFEATURE_H



#include <linux/bitmap.h>

#include <linux/jump_label.h>

#include <asm/hwcap.h>

#include <asm/alternative-macros.h>

#include <asm/errno.h>



/*

 * These are probed via a device_initcall(), via either the SBI or directly
@@ -50,4 +53,84 @@ static inline bool check_unaligned_access_emulated(int cpu) 
static inline void unaligned_emulation_finish(void) {}

#endif



unsigned long riscv_get_elf_hwcap(void);



struct riscv_isa_ext_data {

	const unsigned int id;

	const char *name;

	const char *property;

};



extern const struct riscv_isa_ext_data riscv_isa_ext[];

extern const size_t riscv_isa_ext_count;

extern bool riscv_isa_fallback;



unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);



bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);

#define riscv_isa_extension_available(isa_bitmap, ext)	\

	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)



static __always_inline bool

riscv_has_extension_likely(const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm_volatile_goto(

		ALTERNATIVE("j	%l[l_no]", "nop", 0, %[ext], 1)

		:

		: [ext] "i" (ext)

		:

		: l_no);

	} else {

		if (!__riscv_isa_extension_available(NULL, ext))

			goto l_no;

	}



	return true;

l_no:

	return false;

}



static __always_inline bool

riscv_has_extension_unlikely(const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm_volatile_goto(

		ALTERNATIVE("nop", "j	%l[l_yes]", 0, %[ext], 1)

		:

		: [ext] "i" (ext)

		:

		: l_yes);

	} else {

		if (__riscv_isa_extension_available(NULL, ext))

			goto l_yes;

	}



	return false;

l_yes:

	return true;

}



static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);

}



static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);

}



#endif

arch/riscv/include/asm/elf.h

+1 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
#include <asm/auxvec.h>

#include <asm/byteorder.h>

#include <asm/cacheinfo.h>

#include <asm/hwcap.h>

#include <asm/cpufeature.h>



/*

 * These are used to set parameters in the core dumps.

arch/riscv/include/asm/hwcap.h

+0 −91
Original line number Diff line number Diff line
@@ -8,9 +8,6 @@ 
#ifndef _ASM_RISCV_HWCAP_H

#define _ASM_RISCV_HWCAP_H



#include <asm/alternative-macros.h>

#include <asm/errno.h>

#include <linux/bits.h>

#include <uapi/asm/hwcap.h>



#define RISCV_ISA_EXT_a		('a' - 'a')
@@ -67,92 +64,4 @@ 
#define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SSAIA

#endif



#ifndef __ASSEMBLY__



#include <linux/jump_label.h>

#include <asm/cpufeature.h>



unsigned long riscv_get_elf_hwcap(void);



struct riscv_isa_ext_data {

	const unsigned int id;

	const char *name;

	const char *property;

};



extern const struct riscv_isa_ext_data riscv_isa_ext[];

extern const size_t riscv_isa_ext_count;

extern bool riscv_isa_fallback;



unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);



#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)



bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);

#define riscv_isa_extension_available(isa_bitmap, ext)	\

	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)



static __always_inline bool

riscv_has_extension_likely(const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm_volatile_goto(

		ALTERNATIVE("j	%l[l_no]", "nop", 0, %[ext], 1)

		:

		: [ext] "i" (ext)

		:

		: l_no);

	} else {

		if (!__riscv_isa_extension_available(NULL, ext))

			goto l_no;

	}



	return true;

l_no:

	return false;

}



static __always_inline bool

riscv_has_extension_unlikely(const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm_volatile_goto(

		ALTERNATIVE("nop", "j	%l[l_yes]", 0, %[ext], 1)

		:

		: [ext] "i" (ext)

		:

		: l_yes);

	} else {

		if (__riscv_isa_extension_available(NULL, ext))

			goto l_yes;

	}



	return false;

l_yes:

	return true;

}



static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);

}



static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);

}

#endif



#endif /* _ASM_RISCV_HWCAP_H */

arch/riscv/include/asm/pgtable.h

+1 −0
Original line number Diff line number Diff line
@@ -291,6 +291,7 @@ static inline pte_t pud_pte(pud_t pud) 
}



#ifdef CONFIG_RISCV_ISA_SVNAPOT

#include <asm/cpufeature.h>



static __always_inline bool has_svnapot(void)

{

arch/riscv/include/asm/switch_to.h

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
#include <linux/jump_label.h>

#include <linux/sched/task_stack.h>

#include <asm/vector.h>

#include <asm/hwcap.h>

#include <asm/cpufeature.h>

#include <asm/processor.h>

#include <asm/ptrace.h>

#include <asm/csr.h>