Commit e730c585 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Pass sequential ONO bit to DMCUB boot options



[Why]
IPS ono sequence ordering differs based on the ASIC.

[How]
Detect the ASIC ID revision and set the boot option accordingly. Feed
it through the DCN35 DMUB functions.

Reviewed-by: default avatarSung joon Kim <sungjoon.kim@amd.com>
Acked-by: default avatarRodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ef319dff
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+9 −0
Original line number Diff line number Diff line
@@ -1230,6 +1230,15 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
		break;
	}

	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
	case IP_VERSION(3, 5, 0):
	case IP_VERSION(3, 5, 1):
		hw_params.ips_sequential_ono = adev->external_rev_id > 0x10;
		break;
	default:
		break;
	}

	status = dmub_srv_hw_init(dmub_srv, &hw_params);
	if (status != DMUB_STATUS_OK) {
		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
+1 −0
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ struct dmub_srv_hw_params {
	bool dpia_hpd_int_enable_supported;
	bool disable_clock_gate;
	bool disallow_dispclk_dppclk_ds;
	bool ips_sequential_ono;
	enum dmub_memory_access_type mem_access_type;
	enum dmub_ips_disable_type disable_ips;
};
+1 −0
Original line number Diff line number Diff line
@@ -420,6 +420,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
	boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds;
	boot_options.bits.disable_clk_gate = params->disable_clock_gate;
	boot_options.bits.ips_disable = params->disable_ips;
	boot_options.bits.ips_sequential_ono = params->ips_sequential_ono;

	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
}