Commit e7534e79 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Manivannan Sadhasivam
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dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding 



The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express
Base Specification 4.0. It is designed for root complex applications and
features a single-lane (x1) implementation. Add binding documentation for
it.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251119143523.977085-2-claudiu.beznea.uj@bp.renesas.com
parent 3a866087

Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G3S PCIe host controller



maintainers:

  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>



description:

  Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification

  4.0 and supports up to 5 GT/s (Gen2).



properties:

  compatible:

    const: renesas,r9a08g045-pcie # RZ/G3S



  reg:

    maxItems: 1



  interrupts:

    items:

      - description: System error interrupt

      - description: System error on correctable error interrupt

      - description: System error on non-fatal error interrupt

      - description: System error on fatal error interrupt

      - description: AXI error interrupt

      - description: INTA interrupt

      - description: INTB interrupt

      - description: INTC interrupt

      - description: INTD interrupt

      - description: MSI interrupt

      - description: Link bandwidth interrupt

      - description: PME interrupt

      - description: DMA interrupt

      - description: PCIe event interrupt

      - description: Message interrupt

      - description: All interrupts



  interrupt-names:

    items:

      - description: serr

      - description: ser_cor

      - description: serr_nonfatal

      - description: serr_fatal

      - description: axi_err

      - description: inta

      - description: intb

      - description: intc

      - description: intd

      - description: msi

      - description: link_bandwidth

      - description: pm_pme

      - description: dma

      - description: pcie_evt

      - description: msg

      - description: all



  interrupt-controller: true



  clocks:

    items:

      - description: System clock

      - description: PM control clock



  clock-names:

    items:

      - description: aclk

      - description: pm



  resets:

    items:

      - description: AXI2PCIe Bridge reset

      - description: Data link layer/transaction layer reset

      - description: Transaction layer (ACLK domain) reset

      - description: Transaction layer (PCLK domain) reset

      - description: Physical layer reset

      - description: Configuration register reset

      - description: Configuration register reset



  reset-names:

    items:

      - description: aresetn

      - description: rst_b

      - description: rst_gp_b

      - description: rst_ps_b

      - description: rst_rsm_b

      - description: rst_cfg_b

      - description: rst_load_b



  power-domains:

    maxItems: 1



  dma-ranges:

    description:

      A single range for the inbound memory region.

    maxItems: 1



  renesas,sysc:

    description: |

      System controller registers control and monitor various PCIe

      functionalities.



      Control:

      - transition to L1 state

      - receiver termination settings

      - RST_RSM_B signal



      Monitor:

      - clkl1pm clock request state

      - power off information in L2 state

      - errors (fatal, non-fatal, correctable)

    $ref: /schemas/types.yaml#/definitions/phandle



patternProperties:

  "^pcie@0,[0-0]$":

    type: object

    allOf:

      - $ref: /schemas/pci/pci-pci-bridge.yaml#



    properties:

      reg:

        maxItems: 1



      vendor-id:

        const: 0x1912



      device-id:

        const: 0x0033



      clocks:

        items:

          - description: Reference clock



      clock-names:

        items:

          - const: ref



    required:

      - device_type

      - vendor-id

      - device-id

      - clocks

      - clock-names



    unevaluatedProperties: false



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names

  - interrupts

  - interrupt-names

  - interrupt-map

  - interrupt-map-mask

  - interrupt-controller

  - power-domains

  - "#address-cells"

  - "#size-cells"

  - "#interrupt-cells"

  - renesas,sysc



allOf:

  - $ref: /schemas/pci/pci-host-bridge.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r9a08g045-cpg.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    bus {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie@11e40000 {

            compatible = "renesas,r9a08g045-pcie";

            reg = <0 0x11e40000 0 0x10000>;

            ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;

            /* Map all possible DRAM ranges (4 GB). */

            dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;

            bus-range = <0x0 0xff>;

            interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "serr", "serr_cor", "serr_nonfatal",

                              "serr_fatal", "axi_err", "inta",

                              "intb", "intc", "intd", "msi",

                              "link_bandwidth", "pm_pme", "dma",

                              "pcie_evt", "msg", "all";

            #interrupt-cells = <1>;

            interrupt-controller;

            interrupt-map-mask = <0 0 0 7>;

            interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */

                            <0 0 0 2 &pcie 0 0 0 1>, /* INTB */

                            <0 0 0 3 &pcie 0 0 0 2>, /* INTC */

                            <0 0 0 4 &pcie 0 0 0 3>; /* INTD */

            clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,

                     <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;

            clock-names = "aclk", "pm";

            resets = <&cpg R9A08G045_PCI_ARESETN>,

                     <&cpg R9A08G045_PCI_RST_B>,

                     <&cpg R9A08G045_PCI_RST_GP_B>,

                     <&cpg R9A08G045_PCI_RST_PS_B>,

                     <&cpg R9A08G045_PCI_RST_RSM_B>,

                     <&cpg R9A08G045_PCI_RST_CFG_B>,

                     <&cpg R9A08G045_PCI_RST_LOAD_B>;

            reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",

                          "rst_rsm_b", "rst_cfg_b", "rst_load_b";

            power-domains = <&cpg>;

            device_type = "pci";

            #address-cells = <3>;

            #size-cells = <2>;

            renesas,sysc = <&sysc>;



            pcie@0,0 {

                reg = <0x0 0x0 0x0 0x0 0x0>;

                ranges;

                clocks = <&versa3 5>;

                clock-names = "ref";

                device_type = "pci";

                vendor-id = <0x1912>;

                device-id = <0x0033>;

                #address-cells = <3>;

                #size-cells = <2>;

            };

        };

    };



...