+34
−0
+1
−1
Loading
I/O Machine Check Architecture events may signal failing PCIe components or links. The AER event contains details on what was happening on the wire when the error was signaled. Trace the CPER PCIe Error section (UEFI v2.11, Appendix N.2.7) reported by the I/O MCA. Reviewed-by:Dave Jiang <dave.jiang@intel.com> Reviewed-by:
Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by:
Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com> Link: https://patch.msgid.link/20260114101543.85926-3-fabio.m.de.francesco@linux.intel.com Signed-off-by:
Rafael J. Wysocki <rafael.j.wysocki@intel.com>