Commit e781bffc authored Aug 28, 2024 by Elaine Zhang Committed by Heiko Stuebner Aug 29, 2024

clk: rockchip: Add new pll type pll_rk3588_ddr

That PLL type is similar to the other rk3588 pll types but the actual
rate is twice the configured rate.
Therefore, the returned calculated rate must be multiplied by two.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent 49c04453

drivers/clk/rockchip/clk-pll.c

+5 −1

Original line number	Diff line number	Diff line
		@@ -914,6 +914,9 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned
		}
		rate64 = rate64 >> cur.s;

		if (pll->type == pll_rk3588_ddr)
		return (unsigned long)rate64 * 2;
		else
		return (unsigned long)rate64;
		}

		@@ -1167,6 +1170,7 @@ struct clk rockchip_clk_register_pll(struct rockchip_clk_provider ctx,
		break;
		case pll_rk3588:
		case pll_rk3588_core:
		case pll_rk3588_ddr:
		if (!pll->rate_table)
		init.ops = &rockchip_rk3588_pll_clk_norate_ops;
		else

drivers/clk/rockchip/clk.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -287,6 +287,7 @@ enum rockchip_pll_type {
		pll_rk3399,
		pll_rk3588,
		pll_rk3588_core,
		pll_rk3588_ddr,
		};

		#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \