Commit e787c9c5 authored by Yu Tu's avatar Yu Tu Committed by Jerome Brunet
Browse files

clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver 



Add the S4 PLL clock controller driver in the S4 SoC family.

Signed-off-by: default avatarYu Tu <yu.tu@amlogic.com>
Link: https://lore.kernel.org/r/20230904075504.23263-4-yu.tu@amlogic.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 98949499

drivers/clk/meson/Kconfig

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@@ -144,4 +144,16 @@ config COMMON_CLK_G12A 
	help

	  Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2

	  devices, aka g12a. Say Y if you want peripherals to work.



config COMMON_CLK_S4_PLL

	tristate "S4 SoC PLL clock controllers support"

	depends on ARM64

	default y

	select COMMON_CLK_MESON_MPLL

	select COMMON_CLK_MESON_PLL

	select COMMON_CLK_MESON_REGMAP

	help

	  Support for the PLL clock controller on Amlogic S805X2 and S905Y4 devices,

	  AKA S4. Say Y if you want the board to work, because PLLs are the parent of

	  most peripherals.

endmenu

drivers/clk/meson/Makefile

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@@ -22,3 +22,4 @@ obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o 
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o

obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o

obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o

obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o

drivers/clk/meson/s4-pll.c

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drivers/clk/meson/s4-pll.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */

/*

 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved

 * Author: Yu Tu <yu.tu@amlogic.com>

 */



#ifndef __MESON_S4_PLL_H__

#define __MESON_S4_PLL_H__



#define ANACTRL_FIXPLL_CTRL0                       0x040

#define ANACTRL_FIXPLL_CTRL1                       0x044

#define ANACTRL_FIXPLL_CTRL3                       0x04c

#define ANACTRL_GP0PLL_CTRL0                       0x080

#define ANACTRL_GP0PLL_CTRL1                       0x084

#define ANACTRL_GP0PLL_CTRL2                       0x088

#define ANACTRL_GP0PLL_CTRL3                       0x08c

#define ANACTRL_GP0PLL_CTRL4                       0x090

#define ANACTRL_GP0PLL_CTRL5                       0x094

#define ANACTRL_GP0PLL_CTRL6                       0x098

#define ANACTRL_HIFIPLL_CTRL0                      0x100

#define ANACTRL_HIFIPLL_CTRL1                      0x104

#define ANACTRL_HIFIPLL_CTRL2                      0x108

#define ANACTRL_HIFIPLL_CTRL3                      0x10c

#define ANACTRL_HIFIPLL_CTRL4                      0x110

#define ANACTRL_HIFIPLL_CTRL5                      0x114

#define ANACTRL_HIFIPLL_CTRL6                      0x118

#define ANACTRL_MPLL_CTRL0                         0x180

#define ANACTRL_MPLL_CTRL1                         0x184

#define ANACTRL_MPLL_CTRL2                         0x188

#define ANACTRL_MPLL_CTRL3                         0x18c

#define ANACTRL_MPLL_CTRL4                         0x190

#define ANACTRL_MPLL_CTRL5                         0x194

#define ANACTRL_MPLL_CTRL6                         0x198

#define ANACTRL_MPLL_CTRL7                         0x19c

#define ANACTRL_MPLL_CTRL8                         0x1a0

#define ANACTRL_HDMIPLL_CTRL0                      0x1c0



#endif /* __MESON_S4_PLL_H__ */