Unverified Commit e7a45dec authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'renesas-clk-fixes-for-v7.0-tag1' of... 

Merge tag 'renesas-clk-fixes-for-v7.0-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-fixes

Pull Renesas clk driver fixes from Geert Uytterhoeven:

 - Fix ordering of module clocks arrays on Renesas RZ/V2H(P) and RZ/V2N
 - Remove clocks for watchdogs meant for other CPU cores on the
   Renesas RZ/V2H(P) SoC

* tag 'renesas-clk-fixes-for-v7.0-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
  clk: renesas: r9a09g056: Fix ordering of module clocks array
  clk: renesas: r9a09g057: Fix ordering of module clocks array
parents c3692998 1b4f047d

drivers/clk/renesas/r9a09g056-cpg.c

+18 −18
Original line number Diff line number Diff line
@@ -289,6 +289,24 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -389,24 +407,6 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 14, 4, 14,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,

						BUS_MSTOP(3, BIT(14))),

	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,

drivers/clk/renesas/r9a09g057-cpg.c

+20 −35
Original line number Diff line number Diff line
@@ -280,22 +280,30 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
						BUS_MSTOP(11, BIT(15))),

	DEF_MOD("gtm_7_pclk",			CLK_PLLCLN_DIV16, 4, 10, 2, 10,

						BUS_MSTOP(12, BIT(0))),

	DEF_MOD("wdt_0_clkp",			CLK_PLLCM33_DIV16, 4, 11, 2, 11,

						BUS_MSTOP(3, BIT(10))),

	DEF_MOD("wdt_0_clk_loco",		CLK_QEXTAL, 4, 12, 2, 12,

						BUS_MSTOP(3, BIT(10))),

	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,

						BUS_MSTOP(1, BIT(0))),

	DEF_MOD("wdt_1_clk_loco",		CLK_QEXTAL, 4, 14, 2, 14,

						BUS_MSTOP(1, BIT(0))),

	DEF_MOD("wdt_2_clkp",			CLK_PLLCLN_DIV16, 4, 15, 2, 15,

						BUS_MSTOP(5, BIT(12))),

	DEF_MOD("wdt_2_clk_loco",		CLK_QEXTAL, 5, 0, 2, 16,

						BUS_MSTOP(5, BIT(12))),

	DEF_MOD("wdt_3_clkp",			CLK_PLLCLN_DIV16, 5, 1, 2, 17,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rtc_0_clk_rtc",		CLK_PLLCM33_DIV16, 5, 3, 2, 19,

						BUS_MSTOP(3, BIT(11) | BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -396,26 +404,6 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 14, 4, 14,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rtc_0_clk_rtc",		CLK_PLLCM33_DIV16, 5, 3, 2, 19,

						BUS_MSTOP(3, BIT(11) | BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,

						BUS_MSTOP(11, BIT(1))),

	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,

						BUS_MSTOP(11, BIT(2))),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,

						BUS_MSTOP(3, BIT(14))),

	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -598,10 +586,7 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 
	DEF_RST(7, 2, 3, 3),		/* GTM_5_PRESETZ */

	DEF_RST(7, 3, 3, 4),		/* GTM_6_PRESETZ */

	DEF_RST(7, 4, 3, 5),		/* GTM_7_PRESETZ */

	DEF_RST(7, 5, 3, 6),		/* WDT_0_RESET */

	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */

	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */

	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */