Commit e7bd34a1 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Support explicit L1 cache disabling. 



This reworks the cache mode configuration in Kconfig, and allows for
explicit selection of write-back/write-through/off configurations.
All of the cache flushing routines are optimized away for the off
case.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent ac919986

arch/sh/kernel/cpu/init.c

+7 −4
Original line number Diff line number Diff line
@@ -143,12 +143,15 @@ static void __init cache_init(void) 
		flags &= ~CCR_CACHE_EMODE;

#endif



#ifdef CONFIG_SH_WRITETHROUGH

	/* Turn on Write-through caching */

#if defined(CONFIG_CACHE_WRITETHROUGH)

	/* Write-through */

	flags |= CCR_CACHE_WT;

#else

	/* .. or default to Write-back */

#elif defined(CONFIG_CACHE_WRITEBACK)

	/* Write-back */

	flags |= CCR_CACHE_CB;

#else

	/* Off */

	flags &= ~CCR_CACHE_ENABLE;

#endif



	ctrl_outl(flags, CCR);

arch/sh/kernel/sh_ksyms.c

+4 −3
Original line number Diff line number Diff line
@@ -128,7 +128,8 @@ DECLARE_EXPORT(__movstrSI12_i4); 
#endif /* __GNUC__ == 4 */

#endif



#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)

#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \

	defined(CONFIG_SH7705_CACHE_32KB))

/* needed by some modules */

EXPORT_SYMBOL(flush_cache_all);

EXPORT_SYMBOL(flush_cache_range);
@@ -136,8 +137,8 @@ EXPORT_SYMBOL(flush_dcache_page); 
EXPORT_SYMBOL(__flush_purge_region);

#endif



#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \

	defined(CONFIG_SH7705_CACHE_32KB))

#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \

	(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))

EXPORT_SYMBOL(clear_user_page);

#endif

arch/sh/mm/Kconfig

+16 −3
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
# Processor families

#

config CPU_SH2

	select SH_WRITETHROUGH if !CPU_SH2A

	bool



config CPU_SH2A
@@ -414,8 +413,17 @@ config SH_DIRECT_MAPPED 
	  Turn this option off for platforms that do not have a direct-mapped

	  cache, and you have no need to run the caches in such a configuration.



config SH_WRITETHROUGH

	bool "Use write-through caching"

choice

	prompt "Cache mode"

	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4

	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)



config CACHE_WRITEBACK

	bool "Write-back"

	depends on CPU_SH2A || CPU_SH3 || CPU_SH4



config CACHE_WRITETHROUGH

	bool "Write-through"

	help

	  Selecting this option will configure the caches in write-through

	  mode, as opposed to the default write-back configuration.
@@ -426,4 +434,9 @@ config SH_WRITETHROUGH 


	  If unsure, say N.



config CACHE_OFF

	bool "Off"



endchoice



endmenu

arch/sh/mm/Makefile

+6 −5
Original line number Diff line number Diff line
@@ -4,9 +4,10 @@ 


obj-y			:= init.o extable.o consistent.o



obj-$(CONFIG_CPU_SH2)	+= cache-sh2.o

obj-$(CONFIG_CPU_SH3)	+= cache-sh3.o

obj-$(CONFIG_CPU_SH4)	+= cache-sh4.o

cache-$(CONFIG_CPU_SH2)		:= cache-sh2.o

cache-$(CONFIG_CPU_SH3)		:= cache-sh3.o

cache-$(CONFIG_CPU_SH4)		:= cache-sh4.o pg-sh4.o

cache-$(CONFIG_CACHE_OFF)	:=



mmu-y			:= tlb-nommu.o pg-nommu.o

mmu-$(CONFIG_CPU_SH3)	+= fault-nommu.o
@@ -14,7 +15,7 @@ mmu-$(CONFIG_CPU_SH4) += fault-nommu.o 
mmu-$(CONFIG_MMU)	:= fault.o clear_page.o copy_page.o tlb-flush.o	\

			   ioremap.o



obj-y			+= $(mmu-y)

obj-y			+= $(cache-y) $(mmu-y)



ifdef CONFIG_DEBUG_FS

obj-$(CONFIG_CPU_SH4)		+= cache-debugfs.o
@@ -22,7 +23,7 @@ endif 


ifdef CONFIG_MMU

obj-$(CONFIG_CPU_SH3)		+= tlb-sh3.o

obj-$(CONFIG_CPU_SH4)		+= tlb-sh4.o pg-sh4.o

obj-$(CONFIG_CPU_SH4)		+= tlb-sh4.o

obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o

endif

arch/sh/mm/pmb.c

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ int __set_pmb_entry(unsigned long vpn, unsigned long ppn, 


	ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos));



#ifdef CONFIG_SH_WRITETHROUGH

#ifdef CONFIG_CACHE_WRITETHROUGH

	/*

	 * When we are in 32-bit address extended mode, CCR.CB becomes

	 * invalid, so care must be taken to manually adjust cacheable