Commit e845bb84 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'introduce-phy-mode-10g-qxgmii' 

Luo Jie says:

====================
Introduce PHY mode 10G-QXGMII

This patch series adds 10G-QXGMII mode for PHY driver. The patch
series is split from the QCA8084 PHY driver patch series below.
https://lore.kernel.org/all/20231215074005.26976-1-quic_luoj@quicinc.com/

Per Andrew Lunn’s advice, submitting this patch series for acceptance
as they already include the necessary 'Reviewed-by:' tags. This way,
they need not wait for QCA8084 series patches to conclude review.

Changes in v2:
	* remove PHY_INTERFACE_MODE_10G_QXGMII from workaround of
	  validation in the phylink_validate_phy. 10G_QXGMII will
	  be set into phy->possible_interfaces in its .config_init
	  method of PHY driver that supports it.
====================

Link: https://lore.kernel.org/r/20240615120028.2384732-1-quic_luoj@quicinc.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 041cc86b 5dfabcdd

Documentation/devicetree/bindings/net/ethernet-controller.yaml

+1 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ properties: 
      - usxgmii

      - 10gbase-r

      - 25gbase-r

      - 10g-qxgmii



  phy-mode:

    $ref: "#/properties/phy-connection-type"

Documentation/networking/phy.rst

+6 −0
Original line number Diff line number Diff line
@@ -327,6 +327,12 @@ Some of the interface modes are described below: 
    This is the Penta SGMII mode, it is similar to QSGMII but it combines 5

    SGMII lines into a single link compared to 4 on QSGMII.



``PHY_INTERFACE_MODE_10G_QXGMII``

    Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII

    Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz

    SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved

    through symbol replication. The PCS expects the standard USXGMII code word.



Pause frames / flow control

===========================

drivers/net/phy/phy-core.c

+1 −0
Original line number Diff line number Diff line
@@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface) 
		return 1;

	case PHY_INTERFACE_MODE_QSGMII:

	case PHY_INTERFACE_MODE_QUSGMII:

	case PHY_INTERFACE_MODE_10G_QXGMII:

		return 4;

	case PHY_INTERFACE_MODE_PSGMII:

		return 5;

drivers/net/phy/phylink.c

+8 −1
Original line number Diff line number Diff line
@@ -231,6 +231,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) 
		return SPEED_1000;



	case PHY_INTERFACE_MODE_2500BASEX:

	case PHY_INTERFACE_MODE_10G_QXGMII:

		return SPEED_2500;



	case PHY_INTERFACE_MODE_5GBASER:
@@ -500,7 +501,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, 


	switch (interface) {

	case PHY_INTERFACE_MODE_USXGMII:

		caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD;

		caps |= MAC_10000FD | MAC_5000FD;

		fallthrough;



	case PHY_INTERFACE_MODE_10G_QXGMII:

		caps |= MAC_2500FD;

		fallthrough;



	case PHY_INTERFACE_MODE_RGMII_TXID:
@@ -926,6 +931,7 @@ static int phylink_parse_mode(struct phylink *pl, 
		case PHY_INTERFACE_MODE_5GBASER:

		case PHY_INTERFACE_MODE_25GBASER:

		case PHY_INTERFACE_MODE_USXGMII:

		case PHY_INTERFACE_MODE_10G_QXGMII:

		case PHY_INTERFACE_MODE_10GKR:

		case PHY_INTERFACE_MODE_10GBASER:

		case PHY_INTERFACE_MODE_XLGMII:
@@ -1124,6 +1130,7 @@ static unsigned int phylink_pcs_neg_mode(unsigned int mode, 
	case PHY_INTERFACE_MODE_QSGMII:

	case PHY_INTERFACE_MODE_QUSGMII:

	case PHY_INTERFACE_MODE_USXGMII:

	case PHY_INTERFACE_MODE_10G_QXGMII:

		/* These protocols are designed for use with a PHY which

		 * communicates its negotiation result back to the MAC via

		 * inband communication. Note: there exist PHYs that run

include/linux/phy.h

+4 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ extern const int phy_10gbit_features_array[1]; 
 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN

 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII

 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN

 * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII

 * @PHY_INTERFACE_MODE_MAX: Book keeping

 *

 * Describes the interface between the MAC and PHY.
@@ -168,6 +169,7 @@ typedef enum { 
	PHY_INTERFACE_MODE_10GKR,

	PHY_INTERFACE_MODE_QUSGMII,

	PHY_INTERFACE_MODE_1000BASEKX,

	PHY_INTERFACE_MODE_10G_QXGMII,

	PHY_INTERFACE_MODE_MAX,

} phy_interface_t;
@@ -289,6 +291,8 @@ static inline const char *phy_modes(phy_interface_t interface) 
		return "100base-x";

	case PHY_INTERFACE_MODE_QUSGMII:

		return "qusgmii";

	case PHY_INTERFACE_MODE_10G_QXGMII:

		return "10g-qxgmii";

	default:

		return "unknown";

	}