Commit e8535e2b authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-am62: disable "cpsw3g" in SoC file and enable in board file 



Following the existing convention of disabling nodes in the SoC file and
enabling only the required ones in the board file, disable "cpsw3g" node
in the SoC file "k3-am62-main.dtsi" and enable it in the board (or board
include) files:
a) k3-am62-lp-sk.dts
b) k3-am62-phycore-som.dtsi
c) k3-am625-beagleplay.dts
d) k3-am625-sk-common.dtsi

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Link: https://patch.msgid.link/20251015111344.3639415-2-s-vadapalli@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 1581a732

arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts

+4 −0
Original line number Diff line number Diff line
@@ -181,6 +181,10 @@ &sdhci1 { 
	vqmmc-supply = <&vddshv_sdio>;

};



&cpsw3g {

	status = "okay";

};



&cpsw_port2 {

	status = "disabled";

};

arch/arm64/boot/dts/ti/k3-am62-main.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -738,6 +738,8 @@ cpsw3g: ethernet@8000000 { 
		dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",

			    "tx7", "rx";



		status = "disabled";



		ethernet-ports {

			#address-cells = <1>;

			#size-cells = <0>;

arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -211,6 +211,7 @@ opp-1400000000 { 
&cpsw3g {

	pinctrl-names = "default";

	pinctrl-0 = <&main_rgmii1_pins_default>;

	status = "okay";

};



&cpsw_port1 {

arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts

+1 −0
Original line number Diff line number Diff line
@@ -590,6 +590,7 @@ &cpsw3g { 
		    <&gbe_pmx_obsclk>;

	assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;

	assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;

	status = "okay";

};



&cpsw_port1 {

arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -212,6 +212,7 @@ &sdhci1 { 
&cpsw3g {

	pinctrl-names = "default";

	pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;

	status = "okay";

};



&cpsw_port2 {