Commit e85f4643 authored by Maksim Kiselev's avatar Maksim Kiselev Committed by Jonathan Cameron
Browse files

dt-bindings: iio: adc: Add Allwinner D1/T113s/R329/T507 SoCs GPADC 



Allwinner's D1/T113s/R329/T507 SoCs have a new general purpose ADC.
This ADC is the same for all of this SoCs. The only difference is
the number of available channels.

Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarMaksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20230619154252.3951913-4-bigunclemax@gmail.com


Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent 046dd089

Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/iio/adc/allwinner,sun20i-d1-gpadc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner D1 General Purpose ADC



maintainers:

  - Maksim Kiselev <bigunclemax@gmail.com>



properties:

  compatible:

    enum:

      - allwinner,sun20i-d1-gpadc



  "#io-channel-cells":

    const: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



  clocks:

    maxItems: 1



  interrupts:

    maxItems: 1



  reg:

    maxItems: 1



  resets:

    maxItems: 1



patternProperties:

  "^channel@[0-9a-f]+$":

    $ref: adc.yaml

    type: object

    description:

      Represents the internal channels of the ADC.



    properties:

      reg:

        items:

          minimum: 0

          maximum: 15



    required:

      - reg



    unevaluatedProperties: false



required:

  - "#io-channel-cells"

  - clocks

  - compatible

  - interrupts

  - reg

  - resets



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/sun20i-d1-ccu.h>

    #include <dt-bindings/reset/sun20i-d1-ccu.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    gpadc: adc@2009000 {

        compatible = "allwinner,sun20i-d1-gpadc";

        reg = <0x2009000 0x400>;

        clocks = <&ccu CLK_BUS_GPADC>;

        resets = <&ccu RST_BUS_GPADC>;

        interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;

        #io-channel-cells = <1>;



        #address-cells = <1>;

        #size-cells = <0>;



        channel@0 {

            reg = <0>;

        };



        channel@1 {

            reg = <1>;

        };

    };

...