Commit e8b16c7a authored by Tudor Ambarus's avatar Tudor Ambarus Committed by Mark Brown
Browse files

spi: s3c64xx: switch gs101 to new port config data 



Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port
config data.

Advantages of the change:
- drop dependency on the OF alias ID.
- FIFO depth is inferred from the compatible. GS101 integrates 16 SPI
  IPs, all with 64 bytes FIFO depths.
- use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial
  masks is misleading and can hide problems of the driver logic.

S3C64XX_SPI_ST_TX_FIFO_RDY_V2 was defined based on the USI's
SPI_VERSION.USI_IP_VERSION register field, which has value 2 at reset.

MAX_SPI_PORTS is updated to reflect the maximum number of ports for the
rest of the compatibles.

Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Link: https://msgid.link/r/20240216070555.2483977-12-tudor.ambarus@linaro.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent ad0adac8

drivers/spi/spi-s3c64xx.c

+6 −6
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
#include <linux/spi/spi.h>

#include <linux/types.h>



#define MAX_SPI_PORTS		16

#define MAX_SPI_PORTS		12

#define S3C64XX_SPI_QUIRK_CS_AUTO	(1 << 1)

#define AUTOSUSPEND_TIMEOUT	2000
@@ -79,6 +79,8 @@ 
#define S3C64XX_SPI_INT_RX_FIFORDY_EN		(1<<1)

#define S3C64XX_SPI_INT_TX_FIFORDY_EN		(1<<0)



#define S3C64XX_SPI_ST_RX_FIFO_RDY_V2		GENMASK(23, 15)

#define S3C64XX_SPI_ST_TX_FIFO_RDY_V2		GENMASK(14, 6)

#define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT	6

#define S3C64XX_SPI_ST_RX_OVERRUN_ERR		(1<<5)

#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR		(1<<4)
@@ -1615,11 +1617,9 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { 
};



static const struct s3c64xx_spi_port_config gs101_spi_port_config = {

	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */

	.fifo_lvl_mask	= { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,

			    0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},

	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */

	.rx_lvl_offset	= 15,

	.fifo_depth	= 64,

	.rx_fifomask	= S3C64XX_SPI_ST_RX_FIFO_RDY_V2,

	.tx_fifomask	= S3C64XX_SPI_ST_TX_FIFO_RDY_V2,

	.tx_st_done	= 25,

	.clk_div	= 4,

	.high_speed	= true,